0.18-µm CMOS process enables low-power SoCs

0.18-µm CMOS process enables low-power SoCs

ON Semiconductor has announced a cost-competitive 0.18-µm CMOS process technology dubbed ONC18 — that is said to be ideal for developing low-power and highly integrated digital and mixed-signal SoC devices for automotive, industrial, and medical applications. The ONC18-based solutions will be manufactured at the company’s 8-in. wafer fabrication facility in Gresham, OR, so the process is also expected to prove attractive for designers of U.S. military applications seeking domestic production with ITAR-compliant partners.

The process is suitable for SoCs requiring up to 500 Kgates, offers between four and six levels of metal, and allows designers to integrate 1.8-V core voltages with 3.3-V input/output (I/O). Options for integrated passive devices include resistors and nominal [1.0 femtofarad per micron squared (fF/µm2 )] and high-value (2.0-fF/µm2 ) stackable metal-insulator-metal (MIM) capacitors.

It is supported with a design kit offering comprehensive core, I/O, and memory libraries. Gate densities and power consumptions for high-density core and mixed-signal core cells are 129 Kgates/mm2 and 46 µW/MHz/gate and 120 Kgates/mm2 and 28 µW/MHz/gate, respectively. Memory options include 64-Kbit synchronous single-port and dual-port SRAM and 64-Kbit VIA-programmable ROM.

The company hopes that future development will enable enhanced mixed-signal capabilities and options for higher-voltage handling. The new process is fully compatible with all common digital and analog/mixed signal CAD tools including those from Cadence, Synopsys, and Mentor Graphics. For more information, contact Kirk Peterson at kirk.peterson@onsemi.com or visit http://www.onsemi.com

Christina Nickolas