0.4-V DRAM array technology using twin cells for next generation mobile devices

0.4-V DRAM array technology using twin cells for next generation mobile devices

Hitachi, Ltd. (NYSE: HIT / TSE: 6501) in cooperation with Elpida Memory, Inc. (TSE: 6665), have proposed a new DRAM(*1) circuit design enabling 0.4-V operation. The proposed array employs a twin cell scheme, which uses two conventional DRAM cells to store 1-bit information, and achieves a longer retention time and fast read/write operation under low voltage condition. This technology will be fundamental for designing DRAM, with its large memory capacity, as the low power memory device in next generation mobile information devices.

Enabling the longer retention time and fast read/write operation under low voltage condition

Memory devices used in mobile information devices need to be able to provide both memory capacity to support increasing new functions and contents, as well as low-power consumption, in order to extend battery life. SRAM(*2) is currently the main memory device used in cellular phones, due to its low power consumption features.

There are, however, several issues for its use in future mobile information devices, such as its large cell size which places restrictions on increasing capacity, and the limitation on lowering the operation voltage due to memory cell variation. DRAM, in contrast, is suited to increasing capacity, and is already being employed as the memory device in some mobile devices.