250 exhibits at DAC 07 San Diego

The Design Automation Conference (DAC) is at the at the San Diego Convention Center this year (June 4 to 8) and features over 50 technical sessions covering the latest in design methodologies and EDA tool developments, plus an exhibition area with over 250 EDA, silicon, and IP providers. We have gathered information on a few of the notable exhibitors for you.

IC Manage (Los Gatos, CA), in booth 6977, will demonstrate GDP—said to be the first data management solution to offer design assembly, derivative management, and real-time worldwide delivery. The package includes IT integration for hot backup, high availability, and disaster recovery 24/7, extending the existing revision control, configuration management and multisite collaboration capabilities. Denali Software (Palo Alto, CA) experts will be on hand in booth 6060 to demonstrate their design and verification IP, embedded software, and SystemVerilog tools. This includes IP for PCI Express 2.0 and IOV, memory controller, and PHY IP for DDR1,2,3 and LPDDR DRAM, plus HW/SW IP Platforms for MLC NAND flash.

In booth 4564, Applied Wave Research (El Segundo, CA) will showcase the latest version of its Microwave Office design suite, which offers advanced openness and interoperability, enabling ease-of-use and access to best-in-class tools for shortening RF/microwave product design cycle time.

GateRocket (Bedford, MA) will show PowerTheater-Explorer in booth 2559, which helps SoC designers reduce power early in the design cycle and helps determine hot spots while enabling interactive debug. The company will also demonstrate their RocketDrive hardware and software that lets FPGA designers validate and test their designs before committing to production.

Silicon Navigator (Cupertino, CA), in booth 2179, will demonstrate its Rocket Design Environment with a new schematic editor, RTL power analysis, and SKILL-compatible PCells. It includes tools that CAD developers can use to speed the adoption of the OpenAccess database and customize a design cockpit.

CoWare (San Jose, CA) will feature the latest release of its Virtual Platform product family at booth 3373, which addresses go-to-market strategies and software development for multicore platform-based designs. New features include automated packaging and licensing of a binary executable virtual hardware for distribution in the enterprise and to partners and customers.

Silistix (San Jose, CA) will demo CHAINarchitect, a member of the CHAINworks suite of tools used by SoC architects to quantitatively explore alternative interconnect implementations to meet the system-level requirements.

Chip Estimate (Cupertino, CA) in booth 2464 will show its InCyte chip-planning system that now predicts chip performance along with accurate estimation of die area, power and packaged chip cost, giving users feedback on performance target feasibility along with die area, power, and packaged chip cost. The EnVision timing constraint verification tool from Real Intent (Sunnyvale, CA) will be shown in booth 5260. It verifies all timing constraints, whether they are used for clock crossings or for functional reasons proves the correctness of all paths with exceptions. Also available is Meridian, a next generation clock domain crossing product which verifies the correctness of data crossing clock domains.

Jim Harrison

Exhibits open Monday-Wednesday 9 AM to 6 PM and Thursday 9 AM to 1 PM. For more information see www.dac.com.