The high-efficiency MIPS I6400 CPU IP core combines a 64-bit architecture and hardware virtualization with scalable multi-threading, multi-core, and multi-cluster coherent processing. It targets embedded, mobile, consumer, communications, networking and storage applications.
The CPU core is said to achieve 50% higher CoreMark performance and 30% higher DMIPS compared to leading competitors in its class. Its simultaneous multi-threading (SMT) technology enables execution of multiple instructions from multiple threads every clock cycle. The IPs MIPS Coherency Manager fabric is based on a new coherent interconnect architecture and the core supports multiple independent security contexts and multiple independent execution domains. General availability scheduled for December 2014.
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