64-core tile processor boasts 32-Tbit/s interconnect

64-core tile processor boasts 32-Tbit/s interconnect

Each tile takes only 170 to 300 mW at 600 to 900 MHz

Stemming from research sponsored by DARPA and the National Science Foundation, the TILE64 processor contains 64 full-featured, programmable cores, each capable of running Linux, and is said to provide 10X the performance and 30X the performance-per-watt of the Intel dual-core Xeon processor. The chip uses a mesh network with a communications switch on each processor core, rather than a bus, creating an efficient two-dimensional traffic system for packets. Target markets for the device include the embedded networking and digital multimedia applications.

Each core takes only 170 mW at 600 MHz and is a full-featured processor, capable of running its own operating system, with L1 and L2 caches, and a distributed L3 cache. The chip has five independent 2-D mesh peer-to-peer tile networks, each with 32-bit full-duplex channels. The networks provide tile-to-memory, tile-to-tile, and tile-to-I/O data transfer with 2-Tbit/s bisection bandwidth and 32-Tbit/s interconnect bandwidth.

The processor can H.264-encode two 720p HD streams at 30 fps and runs the SNORT network intrusion detection and prevention system at 10 Gbits/s. It has four DDR2 memory controllers, plus two 10-Gbit/s XAUI, two 10 Gbit/s PCIe, and two 1-Gbit/s Ethernet RGMII interfaces, The chip has an Eclipse-based development system featuring spatial views for selecting a single process or region and a multicore debugger and profiler. (From $435 ea/10,000—samples available now.)

Tilera , Santa Clara , CA
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