PLD serves 32-bit logic
The PML2852 is a folded NAND array like its predecessors in the PML
family. It has 96 wide NAND gates and 52 flip-flops (36 buried), with
unrestricted interconnections among them. Each of six banks of flip-flops
can be clocked independently. An enlarged I/O facility allows the chip to
handle more than 32 inputs and 32 outputs at once, suiting it to DMA and
cache control over asynchronous buses. A single scan-test pin connects
the internal D and J-K flip-flops into a scan loop. A power-down mode
reduces consumption to 50 mW. Power-on reset brings the chip up in a known
state. The company's Snap software, version 1.8, supports the chip. 35-
and 50-ns Tpd versions are available. (PML2852, 84-pin PLCC or J-lead
Cerquad, 35-ns PLCC, $23 ea/1,000–available now.) Signetics Co.,
Sunnyvale, CA Kathryn Douglas 408-991-2339
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