80486-based SBC runs at 50 MHz
Operating at 50 MHz, the I486/50 single-board computer for passive
backplanes has an OPTi 82C493/82C392 write-back chipset and an
auto-sensing BIOS. The chipset offers a 1x CPU clock source, CPU-bus
arbitration, hardware read/write ROM shadowing, and a write-back caching
system. To improve performance, the I485/50 can be ordered with a
256-Kbyte 496 Super Cache daughterboard. The board comes with a
hardware/software programmable, three-position watchdog timer and support
for up to 32 Mbytes of 70-ns DRAM on SIMM modules. It also has an
IDE/floppy controller, two 115-kbaud serial ports, one bidirectional
parallel port, and a battery-backed clock/calendar. Software support
includes DOS/Windows 3.1, OS/2, Unix, Xenix, and SCO Unix. ($1,700
ea/large qty–2 weeks ARO.) I-Bus, A Div. of Maxwell Laboratories, San
Diego, CA John Krill 800-382-4229; in CA, 619-974-8400 Fax
619-268-7863
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