HL4.OCT–RM–Texas Instruments
Software and IC facilitate board-level scan testability
Chip talks to four-wire scan bus and to host computer; C source code
compiles to test program
A dedicated scan-test control chip, along with compilable software and
data files for individual testable chips, reduces the investment necessary
to make a system scan-testable. The 74ACT8990 test-bus controller (TBC)
operates under control of a host microprocessor, connected by a 16-bit
data bus and 5-bit address bus (see diagram). Timing of the host interface
is independent of the scan clock. On the test-bus side, the required JTAG
signals–test clock (TCK), test-mode select (TDS), test-data input (TDI),
and test-data output (TDO)–all connect directly. Six separate TMS signals
allow the chip to control up to six separate scan loops, with a common
test clock. Portable C code for scan-test operation, called Scan Engine,
is under development. The code uses Serial Vector format, an emerging
standard already used by Teradyne's Victory software, and TI's ASSET
diagnostic tool. Files of binary data for all JTAG-compliant TI chips can
be downloaded from TI's bulletin board. Similar information should be
forthcoming from other vendors of scannable chips, including Plessey
Semiconductors, VLSI Technology, Advanced Micro Devices, AT&T, Brooktree,
Fujitsu Microelectronics, Honeywell, I-Cube, Integrated Device Technology,
Intel, Motorola, National Semiconductor, Siemens, Toshiba America, and
TRW. (74ACT8990, 44-pin PLCC, $18 ea/1,000–available now.) Texas
Instruments Inc. Dallas, TX Semiconductor Group (SC-92067)
214-995-6611, ext. 3990
CAPTION:
The 74ACT8990 automates many of the functions of the JTAG scan-test
standard.
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