HL6.OCT–RM–Ramtron
DRAM carries automatic on-chip cache
Last-row read latches in 512 x 4 register, responds in 15 ns to
subsequent reads
Ramtron, a company long involved with the application of ferroelectric
materials in semiconductors, has come up with a 1-Mbit dynamic RAM with
its own cache. Externally, the chip, which the company calls an enhanced
DRAM (EDRAM), is a normal DRAM. Unlike a normal DRAM, however, it saves
the contents of the last row accessed in a 2-Kbit static RAM cache. An
address comparator on the chip determines when the cache is hit or missed.
When a read hit occurs, the access time drops to 15 ns. On a read miss,
the line is refilled and the output is available in 35 ns. Writes always
go to the DRAM array, but on a write hit the cache is automatically
updated to maintain coherency. A metal-mask variant, the DM2212, allows
write/per bit in a 1-M x 4-bit chip. This would be used for parity bits.
The company makes 36-bit SIMMs, DM1M36SJ, that combine eight 1-M x 4-bit
DM2202 and one DM2212. DM2200 is a 4-M x 1 version. (15-ns ICs, $21.78
ea/1,000; 20-ns SIMMs, $180.05 ea/100–samples now.) Ramtron
International Corp. Colorado Springs, CO Communications Dept.
719-481-7000 Fax 719-481-9170
CAPTION:
The -15 on these cached DRAMs refers to the read access time on a hit. A
miss reads in 35 ns.
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