Mips processors spread to higher performance, lower cost
Two new chips range in price/performance from $15 microcontroller to 100+
SPECmark processor
Two new RISC processors, the R4400 and the R3041 promise to push the
price/performance boundaries of the Mips architecture at both ends. The
R4400 is pin-compatible with the R4000, but offers higher clock rates, a
32-Kbyte on-chip primary cache, and a write-back buffer that will
accelerate dumb-frame-buffer graphics. The R3041, a derivative Mips
processor from IDT, challenges the 29000 and i960 families in the
laser-printer and similar embedded-control markets. The fastest initial
grade of the 4400 is 75 MHz external/150 MHz internal, up from 50/100 in
the R4000. The external bus rate has additional division ratios available
so the part can run in any existing R44000 socket. The grades announced
are 50/100, 67/134, and 75/150 MHz. Both 5.0-V and 3.3-V parts will be
available. On-chip instruction and data caches are increased to 16 Kbytes
each in the R4400. The SC and MC parts, which come in 447-pin PGA
packages, manage external secondary cache up to four Mbytes. As with
the R4000, there is a PC version of the R4400 in a 179-pin PGA, which does
not support secondary cache. Although the initial chips will be the same,
whichever the package, there will be stronger motivation for a separate
PC chip this time, because the R4400 die is pad limited at the initial 0.6
microns process technology. The 2.3 million transistors fit in a 15 x 10.
5-mm core, but the full pad ring takes 15.5 x 11.9. Toshiba, the most
recent addition to the list of Mips silicon partners, plans initial
production in a 0.4-micron process, for 3.3 V operation only. A separate
PC chip in this process would increase the output/per wafer dramatically,
even if there were no increase in yield. Toshiba plans to be in production
by the end of this year. NEC, which has often been first out of the gate
with new turns, promises engineering samples in the first quarter,
production in the second. NEC's price projections in quantity range from
$1250 to $1,750.
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The addition of a write-back buffer in the 4400 should improve the
performance of simple computers at the PC end of the range, such as Iris
Indigo and ARC PCs, which use dumb frame buffers. These depend on the CPU
for pixel swapping, which requires frequent memory writing to the frame
buffer entailing pipeline stalls in R3000 and R4000 machines.
Performance predictions from Mips have been close in the past. If they are
right this time, the R4400 should be a lot faster than Intel's Pentium.
With ARC chipsets available, it should be price-competitive with
Pentium-based PCs also. Thus it has a chance in the very high end of the
PC market, where machines may run Windows NT. However, to have a prayer in
the mass PC market, Mips must depend on Microsoft to make NT a household
operating system, as well as a household word. The R4400 has enough
horsepower to execute peripheral functions, such as modems, in software.
That opens the possibility of very simple machines with almost no ICs in
them beyond a microprocessor and memory. Small and cheap Integrated
Device Technology and LSI Logic, among the Mips partners, have been most
active in generating embedded variants of the Mips architecture. The most
recent from IDT, the R3041, takes over from the company's R3051 as the
cheapest Mips derivative. The R3041 shares pinout with the 3051 and 3081
in an 84-pin PQFP. A single board design, and a single software effort,
can produce machines at three prices. There is no floating-point hardware.
The vendor supplies floating-point trap routines. The R3041 has on-chip a
2 Kbyte instruction cache and a 512-byte data cache. Its off-chip traffic
has variable bus width, directly talking to 8, 16, and 32-bit data buses.
There are 4-word deep read and write buffers (See die photo) The MMU is
that of the basic, not extended, R3051. It keeps attributes such as
cacheable or non cacheable status, as well as width, for each segmant. The
MMU handles virtual-to-physical translation without recourse to a TLB.
Only the high 3 bits of the virtual address are used to determine the
character of the address. For systems requiring more, extended versions of
the 3051 family, or full-blown R3000/R4000 processors, must be used. The
R3041 comes in 16 and 20-MHz speed grades ($15 ea/high volume–samples end
of year.)Call Bob Rowe at IDT, 408-492-8631. For information on the R4400,
call the individual chip vendors
The R3041 is a $15 R3000 variant, aimed at low-end laser printers and X
terminals. Its relatively rigid MMU is tailored to embedded systems.
The R4400 is pad limited. There is a space around the logic inside the
pad ring. The two 16-Kbyte caches are clearly vsible.
Like its predecessor, the R4400 comes in a 179-pin package for low-cost
machines without a secondary cache, and a 447-pin package with full
controll for off-chip secondary cache up to 4 Mbytes.
Toshiba rc: Annette Birkett 714-455-2000 or Information
800-879-4963
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