VHDL tool speeds high-level design
Version 3.0 of the VHDL System Simulator offers full gate-level timing
support with Zycad's XP accelerator, dynamically linked C models and
better stimulus management, and a comprehensive 3-D debugging environment.
In addition, version 3.0 employs a hierarchical browser/editor, new error
windows, and an improved waveform display. The software also includes
back-annotation of timing delays through the Standard Delay Format as well
as a checkpoint/restart feature. The VHDL System Simulator V3.0 shares a
common VHDL analysis capability with the company's synthesis tools and
runs on the most widely used Unix workstations. (From $24,000–available
now.) Synopsys, Inc., Mountain View, CA Lois DuBois 415-694-4255 Fax
415-965-8637
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