At ISSCC: Pushing the current limits

OL1.JAN–ISSCC–rm

At ISSCC:
Pushing the current limits

Several chipmakers are using this year's International Solid State Circuits Conference* to show chips that press beyond current limitations in transistor counts, low power, memory, and microprocessors. For instance, at the plenary session, a paper by researchers at IBM, Analog Devices, and Auburn University explores the possibility of speed advances using silicon-germanium heterojunction bipolar transistors (HBTs). An experimental die has integrated 0.25-micron CMOS with 60-GHz fmax HBTs in a Si-Ge ECL-BiCMOS structure. Since HBTs have existed only since 1987, this certainly represents encouraging progress. Furthermore, the researchers say reliable manufacturing on 200-mm wafers is near fruition. A 12-bit, 1-GHz digital-analog converter using HBTs dissipates 1 W.
Another paper at the plenary session, by Eric Vittoz from Switzerland, will deal with ultra-low-power techniques used in the wristwatch industry, now becoming of wider interest. And Hiroyuki Mizuno of Matsushita will discuss obstacles and opportunities in the merger of home electronics and computer technologies.

Memory
Matsushita, Mitsubishi, and Oki Semiconductor will all present 256-Mbit dynamic RAMs. All three were fabricated in 0.25-micron CMOS with cells about 0.6 x 1.2 mm. Dies are over 12 x 22 mm.
Most unusual of the three DRAMs, Matsushita's is a 100-MHz serial FIFO for motion-picture storage. It operates at 73 mA current. No separate refresh occurs.
Mitsubishi's chip has 34-ns row access and normal organization. Leakage through the cell-access transistors is reduced by a boosting the ground of the sense circuits.
Oki's example is a cached, synchronous RAM organized in 32 interleaved banks, each with one Kbyte cache. It achieves a 125-Mbyte/s data rate. This is a natural outgrowth of Oki's current self-cached offerings.
The largest nonvolatile memory this year is a 64-Mbit flash from NEC. A single-supply 3.3-V device, it has 50-ns read access. With a 0.4-micron process, it is not nearly as packed as the cutting-edge DRAMs. The square chip is 19.3 mm on a side, close to the long dimension of the narrow DRAM chips. Even so, the density achieved shows that flash is rapidly becoming a viable medium for bulk storage.
In static RAMs, efforts to improve bandwidth over what could be achieved by process alone will show in papers from Motorola and IBM. Motorola's 16-Mbit BiCMOS cache achieves 220 MHz with 2-stage wave pipelining and a phase-locked loop self-timed generator. Its interface is Gunning Transistor Logic (GTL).
From IBM Microelectronics a 64-Mbit four-way-set-associative cache RAM appears to the outside like a three-port. It does this by internally multiplexing 5-ns accesses to separate ports.
An anomaly in the SRAM session, included because the bulk of the chip is memory, is a SIMD video processor with 64 processing elements, with 2 Mbits of memory on the same chip. It does 3.84 GIPS, of whatever its instructions are, and has an internal 1.3-Gbyte/s processing bandwidth. This may well be one significant wave of the future. As memories get larger, simple dedicated processors can be sprinkled throughout with very little silicon penalty.

Microprocessors
The clock-rate champion this year is NEC, with a small chip running 500 MHz. In 0.4-micron CMOS, the 200,000-transistor chip includes two-stage pipelined cache logic, an 8-stage pipeline, and 1.8-ns register access. Its interface to the world uses 1-V swings.
Intel chose ISSCC as the forum to discuss its second-generation Pentium. The new processor will still be BiCMOS, diverging from an industry almost unanimous in its use of CMOS for microprocessors, even at the highest clock rates.
Intel uses a 0.6-micron process with four metal layers to get die size down, as well as to reduce clock skew and on-chip voltage drops. The processor is said to achieve 100 SPECint at 100 MHz, while dissipating 8 W.
The dissipation, improved from the current Pentium, is helped by the chip's ability to turn the clock off to unused parts of the chip. In addition, the clocking system supports fractional bus-to-core frequency ratios.
A joint paper from Toshiba and Silicon Graphics will reveal an aggressively superscalar Mips Technology processor. Issuing up to four instructions/clock, the chip can execute a peak of 300 million instructions, integer or floating-point, per second at 75 MHz.
As with all superscalar designs, the actual rules governing what instructions can start simultaneously have a profound effect on actual performance. No SPEC projections are alleged for this chip yet. In 0.5-micron CMOS, the square chip measures 17.3 mm on a side.
Both Mips Technology and IBM will discuss chips aimed at low-power consumption, rather than ultimate performance. Hewlett-Packard departs from form with an on-chip cache in a highly integrated chip that connects directly to main memory, I/O, and other processors in a multiprocessing system.
–Rodney Myrvaagnes

*This year the International Solid State Circuits Conference will take place in the San Francisco Marriott, February 16 to 18. For more, contact Diane Suiters, Courtesy Associates, 655 15th St., NW, Suite 300, Washington, DC 20005, 202-639-4255.

CAPTION:

Various nonvolatile memory technologies have shown different progressions over five years.