State machine editor
simplifies FPGA designs
The Active-State Editor is a state machine editor that allows designers to
directly simulate the design graph and view the flow of control signals on the
graph. The tool produces device-independent CPLD and FPGA designs, and allows
for graphical entry of highly complex designs, including hierarchical bus-based
state machines and mixed Moore and Mealy machine designs. The state machine
designs are automatically converted into ABEL or VHDL output formats to
facilitate logic synthesis into target devices. ($795–available now.)
ALDEC, Inc.
Newbury Park, CA
Gregor Siwinski 800-532-2533
Fax 805-498-7945
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