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Virtual Sockets promise more-flexible system-on-chip designs

Virtual Sockets promise more-flexible system-on-chip designs

The Virtual Socket Interface Alliance (VSIA), founded last September,
has published its Architecture Document, version 1.0. It attempts to solve
a problem inherent in vast ASICs. When the chip gets big enough to carry
an entire system, a designer is now restricted to subsystems that can be
licensed from the chosen ASIC vendor. At the same time, holders of subsystem
designs can only sell their intellectual property through the ASIC houses,
who are not obliged to deal with them.

The Document defines “Virtual Components” (VCs), which are
block functions that may be licensed for use in ASIC design. It attempts
to specify the information needed at the interface to make a VC work with
the rest of a system, without revealing internal design details.

Referring to the diagram , all elements of VC vendor design are
on the left of the VSIA block. The work of the integrator, or ASIC designer,
is on the right. VSIA is concerned with all the elements of information
transfer between the two design flows.

Virtual Sockets promise more-flexible system-on-chip designs

The design flows for creation of Virtual Components (left) are completely
separated from the user design flows (right) with VSIA-specified information
connecting the two.

The Alliance does not attempt to displace existing technologies for
cell reuse. Rather, it will include existing reuse standards that meet
its criteria, provided that the owner agrees not to assert intellectual-property
rights in the VSIA domain. However, it hopes to encourage convergence of
these proprietary standards toward a universal interface.

The Document groups VCs as Soft, Firm, or Hard, according to how strongly
they are targeted to a specific process. Soft VCs are delivered as synthesizable
HDL, while Hard VCs come optimized for power, size, or performance, and
mapped to a specific technology, physical layout, or combination of the
two. Hard is much less risky for intellectual property loss, but Soft is
adaptable to many more users. Firm VCs are compromises between Hard and
Soft.

Version 1.0 of the document leaves many transfer formats to be determined.
Nonetheless, the 69 pages give an outline form to the whole, and indicate
the thinking of the committee. If successful, the VSIA should foster a
booming commerce in design intellectual property. The long list of companies
already signed on indicates the seriousness of the effort.

Membership is open to any corporation with an interest in the development
and promotion of open standards used in the design of system chips. For
more information, visit http://www.vsi.org or e-mail info@ip-net.org.

–Rodney Myrvaagnes

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