HP, Intel offer first glimpse of
64-bit µP architecture

Intel (Santa Clara, CA) and Hewlett-Packard (Palo Alto, CA) recently revealed a few details of the new microprocessor architecture, IA-64, that they have been jointly developing. The collaboration was announced years ago, but the companies kept a tight lid on the developments, which resulted in a stream of mostly unfounded rumors.

IA-64 will contain hardware to make it run both x86 and PA-RISC binaries without recompilation, but its fundamentals are new, and only new code will be optimal. It exploits aspects of post-RISC architectural work, such as speculative and predicated execution, brought together under the acronym EPIC (for “explicitly parallel instruction computing”). Much of EPIC demands massive logic resources, and the first chip, called Merced, will only appear when a 0.18-µm process is well in hand at Intel, perhaps midyear 1999.

IA-64 specifies 128 64-bit general registers, and 128 floating-point registers, probably 80-bit for compatibility with the Pentium (now called IA-32) architecture. It also specifies multiple execution units in both the floating-point and integer parts (see diagram ). Process shrinks will allow more execution units to be added in later generations.

The new Intel-HP architecture, IA-64, does not limit the number of
execution units, but provides a way of using more than early silicon will hold.

Instruction fetches are 128 bits wide, but IA-64 is not a VLIW model. Instead each fetch brings in three instructions. Even with the same number of op codes as normal RISC instruction sets, 21 bits would be needed to specify two sources and a destination, rather than the 15 normally used, so the instruction words are longer than 32 bits. How much longer has not been revealed.

In addition to op codes and register addresses, the instructions include predicates. The architecture allows for 64 1-bit predicate registers, which are set by comparison operations. The predicates are assigned by the compiler.

At run time, an instruction's predicate must be true, or the instruction acts as a no-op. Predicates allow the compiler to eliminate most branching instructions.

The IA-64's compiler analyzes code, searching for parallelism, and arranges sequential blocks by means of the predicates. In a VLIW machine, the compiler would be forced to group the operations that execute simultaneously without regard to run-time changes, resulting in a lot of wasted execution. On the other hand, with EPIC the predicates tell the hardware which pending operations are independent, so they can be issued to an execution unit without the kind of dependency checking a superscalar RISC processor must do.

Speculation is another major feature of EPIC. A speculative load instruction tests for exceptions, but rather than jumping to an exception handler it generates an “exception token” that propagates forward in the same block of code. A separate instruction checks for the presence of an exception token later on.

The point of the speculative load is to separate the load from the exception handling it may entail and to allow the load to be issued before a branch. The checking instruction is only encountered in the stream where it is needed, and is eliminated if it is in a branch not taken.

These new features appear to give IA-64 the potential to use many more execution units in future chips than conventional superscalar architectures could ever usefully schedule. As with most advances, it depends on its own time to make it possible. The silicon for the massive register file would not have been available in earlier processes, nor could the compiler technology of a few years ago been able to use EPIC.

Backward compatibility with both IA-32 and PA-RISC will be included in Merced with unspecified hardware. It seems certain, however, that recompilation will be needed to approach the potential performance of the new architecture. Furthermore, Merced will only be used in high-end servers and HP workstations at first.

Contrary to previous practice, Intel asserts that IA-64 will not immediately supplant the IA-32 architecture. Intel instead plans to continue the IA-32 through two more generations at much lower prices than Merced. Hewlett Packard will phase its PA-RISC customers into the new architecture gradually as well.