New architecture combines FPGA and CPLD cells with embedded RAM

Altera (San Jose, CA) expects its coming 0.25-µm six-metal-layer process generation to achieve densities of 500,000 gates in its RAM-based programmable logic. To make effective use of this capacity, and that of the subsequent 0.18- and 0.15-µm shrinks, the company has devised a new architecture, dubbed “Raphael,” that combines cells from its prior Flex FPGA and MAX CPLD families, along with dual-ported RAM arrays.

The three kinds of cells are grouped in a “MultiCore Array,” with each core consisting of one of each kind of cell. These are joined with a four-level hierarchy of interconnection, one level above the three in the company's Flex 6000 family.

The lookup-table (LUT) portion is a Flex EPF6016, while the product-term part is a MAX EPM7128; the memory is an enhanced version of the embedded array block (EAB) used in the Flex10K family. The EAB enhancements include variable width–by 1, 2, 4, 8, or 16 bits. The dual-port feature allows the memory to be used as FIFOs.

The four-level interconnect scheme and the use of product-term cells uses extra metal layers more effectively than a pure RAM-based FPGA, letting the density grow faster with process shrinks than would the Flex10K family. At 0.18 µm with six metal layers, the capacity should reach a million gates by the end of 1999 with no reticle size increase.

The cells of Altera's MultiCore architecture each include a previous
FPGA, a previous CPLD, and a dual-port RAM

Current Altera software cannot deal with both product-term and LUT cells, nor is it designed to handle million-gate designs. The company is developing software that it hopes will preserve the time-to-market advantage that smaller programmable devices have had vis a vis ASICs.

A software feature called CoreSyn is a hierarchical-synthesis algorithm that maps each logic function in a design to the most suitable cell type. Other features will include multithreading, improved integration of megafunction cores, and expanded access to user features over the Internet.

The initial Raphael devices should be available in the first half of 1999. They will be half-million-gate parts. When the process shrinks to 0.15 with seven metal layers, the company expects to pack two million gates in the largest die. For more information, visit http://www.altera.com.