Microprocessor and memory
advances coming at ISSCC

The International Solid State Circuits Conference will convene at the San Francisco Marriott on Thursday, Feb. 5, and run through Saturday.* Key digital advances will include a 1.1-GHz microprocessor and a host of other developments.

Microprocessors

Three of the six papers in the microprocessor session come from IBM. The king of the clock-speed hill runs an integer subset of the PowerPC instruction set at 1.1 GHz with 1.8-V power. It is a single-issue machine with a four-stage pipeline, and includes a full-speed internal scan loop with a divide-by-sixteen interface to the outside tester. The circuitry is dynamic.

Another PowerPC implementation is the first use of IBM's recently patented process for laying copper interconnects. The dual-issue processor occupies 40 mm ² in a 0.2-µm CMOS process with six copper layers. The pitch of the lowest layer is 0.63 µm.

The new process results in a clock rate of over 500 MHz at room temperature,and 480 MHz at 85°C. This appears to have immediate commercial application and will probably be announced as a product soon.

Copper interconnect promises to be a hot topic at ISSCC and elsewhere as RC delays become more of a problem. Texas Instruments (Dallas, TX) has also been working on copper interconnection at the company's Kilby Center labs. The lab has produced prototype chips in which the copper is insulated by an ultra-low-k dielectric material called xerogel. TI's prototypes came too late to be reported at ISSCC.

The third IBM paper, also of commercial use, is an AS400 implementation with hardware multithreading. Multithreading in this case adds 10% to the silicon area in content-addressable memory and extra general registers.

When one thread starts a memory operation, another thread may be ready in other registers and dispatch without skipping a beat. As long as threads are kept ready to go, memory latency is hidden. A throughput increase of up to 30% resulted in both uni- and multi-processing machines.

Digital Semiconductor (Hudson, MA) is also on the edge of technology with a discussion of area/performance tradeoffs in an out-of-order instruction-cue circuit. Also commercial, this circuit appears in a 600-MHz Alpha microprocessor.

Another Alpha paper is scheduled in the Multimedia session. This one describes a 667-MHz processor featuring a 64-bit integer multiplier that completes in 6 ns. It occupies about 100 mm ² in 0.28-µm CMOS.

Both Intel (Santa Clara, CA) and AMD (Sunnyvale, CA) have x86 papers. Intel has boosted P6 performance to 450 MHz with support for up to 2 Mbytes of L2 cache via a dedicated port. AMD has made micro-architectural improvementsin the K6, which fits on an 80-mm ² die and supports a 100-MHz socket 7 interface. By contrast, the P6 in the Intel paper occupies 131 mm ² .

Chip-to-chip interfaces

Although “system-on-a-chip” is a common buzzword these days, there will continue to be systems too big for a chip for the foreseeable future. A five-paper session will be devoted to the problems of interchip transfer.

Two of the papers concern the revised Rambus standard (see Electronic Products , Dec. 1997, p. 25), which will be used in future Intel motherboardsets. The joint Rambus/Intel paper presents the interface as a general-purpose connection, not limited to memory.

Another paper, from Fujitsu Labs (Kawasaki, Japan) describes a partial-response-detection scheme to deliver a global timing reference with zero delay across a system. The other papers describe interfaces for other high-speed DRAMs.

Memory

This year, for the first time, DRAM macrocells are a part of the proceedings, represented by two papers. This indicates the coming importance of embedded DRAM in systems that truly can be implemented on one chip.

The largest DRAM chip this year, from Fujitsu (Kawasaki, Japan), is 1 Gbit in size. It is a synchronous DRAM that occupies 505 mm ² in 0.18-µm technology.

A 4.5-Mbit SRAM from Hitachi (Tokyo, Japan) achieves a 1.8-ns access and 550-MHz synchronous speed using NMOS sense amplifiers, but no bipolar circuits. Other SRAM papers include specialized organizations for cache memories.