Copper is coming
to ICs

Although IBM will be alone with commercial copper-interconnected ICs
for the near future, the company will not hold that honor forever. Several
companies have reported laboratory success with copper processing, but
no operating ICs.

Copper interconnect is a technology whose time must come, and soon.
As wire cross sections get ever smaller with each process shrink, the RC
delays on complex ICs become worse, canceling to some degree the gains
from shorter distances.

IBM (Hopewell Junction, NY) took the lead on everybody with its announcement
in November of a commercial copper process. The company will probably announce
a copper-connected PowerPC microprocessor this month. However, Motorola
(Austin, TX), NEC (Kanagawa, Japan), and Texas Instruments (Dallas, TX)
are hard at work on copper technologies of their own, as evidenced by papers
at the recent International Electron Devices Meeting in Washington, DC.

Copper's resistivity is a little over half that of the commonly used
copper-doped aluminum. Copper also seems to have improved stability with
respect to electromigration, with measured mean time to failure between
10 and 100 times that for aluminum.

Copper cannot just be substituted in existing processes for two reasons.
It will diffuse through silicon and poison surrounding transistors if not
contained. Also, it does not take well to plasma etching, currently used
to remove unwanted metal between conductors.

Instead, damascene processing must be used. This does not mean that
future ICs will look like antique shotgun barrels, but that the copper
is inlaid in trenches and pits (for vias) previously etched in the oxide
insulating. To prevent copper diffusion, a thin layer of barrier material,
such as titanium nitride, is vapor deposited in the grooves first.

The other half of the RC duo requires materials with the lowest possible
dielectric constant (k). Texas Instruments has been experimenting with
xerogel, a sort of foamed silicon dioxide, with k tunable from 1.3 to 3.0.
The value of k is lower with higher porosity (see diagram ). The
company has succeeded in putting 0.3-µm copper lines in xerogel trenches.

Texas Instruments researchers produced this test structure,
which combines a xerogel dielectric and copper conductor.
The two materials minimize RC interconnect delay in prospective ICs.

In the TI process, the xerogel, adhesion layer, and oxide layer were
laid down and the trenches etched to the bottom of the xerogel. The oxide
lining shown was deposited in some test structures and omitted in others.
The titanium/titanium-nitride barrier layer went in next, with a small
amount of copper. Then the trench was filled with copper by electroplating.
Chemical-mechanical polishing (CMP) then flattened the surface and removed
any copper deposited outside the trench.

NEC experimented with hydrogen silsesquioxane (HSQ) as a dielectric,
with the dielectric constant ranging from 2.7 to 3.0. HSQ is degraded by
residues from the CMP required by the copper. The paper reported successful
methods of cleaning up this problem, so the company will be able to use
HSQ with copper interconnections if it so desires.

Motorola has integrated six layers of copper metallization on a CMOS
structure with 0.2-µm transistors. The researchers used dual-damascene
processing, with a layer of vias and a layer of trenches etched in the
oxide at one time. Only one fill and CMP step is required for both. Motorola
also used titanium nitride as the diffusion barrier.

It is hard to predict which of these companies is closest to a production
copper process, but they all seem to be well behind IBM. Surely IBM's success
will force increased investment in copper technology by any company that
hopes to be a player in future silicon logic. For more information from
IBM, visit http://www.chips.ibm.com. For more information
from NEC, visit . For more information from Motorola, visit http://www.mot-sps.com. For
more information from Texas Instruments, visit http://www.ti.com.