Enhanced CMOS process gives
improved analog performance

A supplier of analog and mixed-signal ICs, IMP (San Jose, CA) has patented a production-tested process for manufacturing zero-threshold p-type MOSFETs. The ability to produce such transistors should lead to the development and production of better-performing analog ICs. The benefits–including higher dynamic range, lower transconductance, lower noise, and greater efficiency–will provide better performance for battery-powered portable equipment.

The process requires an additional ion implantation over that of the standard approach. The p-type MOSFET devices can be created either individually or all at once, and existing zero-threshold nMOS channels are masked so they remain unaffected by this step.

Prior to ion implantation, MOSFETs have an inherent threshold voltage. For nMOS devices, this native threshold varies from ­0.2 to +0.2 V, the voltage range that characterizes the zero-threshold devices.

However, for p-type MOSFETs, the native threshold ranges from ­1.6 to ­1.8 V. In a standard CMOS process, ion implantation shifts this range to ­0.6 to ­1.1 V. The additional ion implantation performed by IMP moves the threshold voltage a second time, placing it at ­0.2 to +0.2 V. These zero-threshold p-type MOSFETs can then be combined with n-type MOSFETs to create low-threshold complementary pairs.

In the past, the use of a second implantation step was deemed impractical because it typically resulted in punch-through, where an applied voltage causes the FET's drain to enlarge until it contacts the source. IMP's technique, described in U.S. Patent Number 5,493,251, describes a method of creating zero-threshold p-type MOSFETs that are not “soft” and do not suffer from a high amount of source-to-drain leakage. The technique has been employed successfully in the company's C1210 CMOS process, which was used to manufacture nearly 10 million units of a read-channel IC for the Iomega ZIP drive.

In addition to describing details of the IC fabrication process, the patent includes claims of various circuit configurations using complementary-pair transistors in amplifier and analog switch designs. For more information, contact David Gillooly of IMP at 408-432-9100 or visit http://www.impweb.com.