Design Automation Conference showcases
Web power, physical design, and more

Visitors to this year's Design Automation Conference in San Francisco
can glimpse the latest innovations in EDA software for board and chip-level
design. Vendors will demonstrate recent twists in Web-based design, which
promise fast access to up-to-date component data, enhanced design analysis,
and greater access to design data.

In addition, exhibitors will be highlighting improvements in physical
design software. These products address the challenges of routing interconnects
in complex chip packages, boards, and MCMs.

Designers of programmable-logic devices will have a chance to see demonstrated
an embedded synthesis environment that integrates RTL floorplanning and
partitioning with logic synthesis. PLD designers will also discover design
tools supporting recently introduced families of low-cost FPGAs.

ASIC designers may be tempted by analysis software that accounts for
peak power conditions and HDL simulators that offer lower cost or new debug
and editing features. Another tool being shown automates the process of
converting C-based algorithms to VHDL or Verilog.

Board and MCM design

InfoQuick (Irvine, CA) will be introducing WebStir for Workgroups,
a tool that gives designers access to the latest component information
available on the Web. Operating under Windows 95/NT, the software allows
users to get data from many different Web sites without having to launch
a Web browser.

Downloaded information is readily available to individuals or teams
who can access it from the local database where parts documentation is
stored. Pricing for an annual subscription starts at $12,000 for a minimum
system, which includes a server and two floating licenses.

VeriBest (Boulder, CO) will show Signal Vision, the latest addition
to its Discovery tool suite for designing high-speed pc boards. Signal
Vision gives the designer the capability to perform what-if analysis at
the conceptual stage of design and to do simulation throughout the layout
process. Discovery is available for Windows NT with prices starting at
$18,000.

PADS (Marlborough, MA) will exhibit PowerBGA, a high-density
interconnect solution for Windows 95/NT that automates the process of creating
interconnections between a bare die and pc board. The software supports
the design of BGAs, chip-scale packages, laminate-based MCMs, and chip-on-board
substrates.

Features include netlist integration, automatic wirebond fanout, bare-die
definition, and an advanced packaging toolbox with specific chip package
functions. Pricing ranges from $15,000 to $35,000, with the product scheduled
to ship in the fourth quarter.

Tanner EDA (Pasadena, CA) will introduce its MCM Pro design suite
for MCM design, layout, verification, and simulation. The tool suite automates
many time-consuming, error-prone design entry tasks by interfacing with
industry-standard formats.

For example, the S-Edit schematic-entry tool automatically creates die
symbols with pin names by using data contained in a DIE exchange format
file. Priced from $19,950, the software is available for Windows 95/NT
and Sun/Sparc platforms.

Zuken-Redac (Santa Clara, CA) will show Route Editor 5000 Version
9.0, a routing tool for pc-board and MCM design. The tool uses any-angle
autorouting to achieve 100% route completion using the minimum number of
layers. In addition, a pull-tight capability changes orthogonal tracks
to minimize the length of route connections.

Other features include an intuitive user interface, pin swapping, and
on-the-fly route-width changing. Available for Windows 95/NT and Unix,
the program comes in two versions: the basic Route Editor 5000 Version
9.0 costs $14,960; a high-speed version, Route Editor 5000HS Version 9.0,
costs $23,936.

Xynetix (Fishers, NY) will exhibit its Interconnect Compiler
autorouting module for its Encore Version 1.4 advanced-IC-package design
software. The program combines a single-layer any-angle autorouter and
automatic net assignment capabilities to autoroute monolithic ICs (see
Fig. 1 ).

Fig. 1 . Interconnect Compiler from Xynetix provides automatic
autorouting for single-chip IC packages including flip-chips and BGAs.

The module is effective for both wirebonding and flip-chip applications
in various package styles, including BGAs and chip-scale packages. The
program runs under HP, Sun, and Windows NT platforms, and is priced from
$20,000.

Programmable-logic design

Synplicity (Sunnyvale, CA) will be showing what it claims to
be the first embedded synthesis environment. Aimed at high-density and
complex programmable-logic designs, HDL Floorplanner and HDL Partitioner
work from within the company's Synplify synthesis tool (see Fig. 2 ).

Fig. 2 . Synplicity's floorplanning and partitioning tools–HDL
Floorplanner and the HDL Partitioner–work from within the company's
synthesis tool, providing an embedded synthesis environment for
programmable-logic design.

Using a common graphical user interface with drag-and-drop commands,
HDL Floorplanner performs RTL floorplanning for a single programmable device,
while HDL Partitioner partitions large designs across multiple devices.
The HDL floorplanner can be invoked after language compilation occurs with
Synplify but prior to technology mapping.

As a result, the user's floorplan knowledge can be fed back into synthesis,
producing more optimized and predictable results. Prices for HDL Floorplanner
and HDL Partitioner start at $17,000.

OrCAD (Beaverton, OR) will demonstrate Version 7.2 of the OrCAD
Express system-level and programmable-logic design software, which now
supports the low-cost “ASIC replacement” FPGAs such as Xilinx
Spartan and Actel MX devices.

A number of other enhancements are also provided, including additional
VHDL language constructs to design and debug digital models, and forward
and backward ECO support for Cadence's Allegro pc-board-layout system.
OrCAD Express is priced at $5,995.

ASIC design

Sente (Acton, MA) will showcase a new feature of its Watt Watcher
power analysis tool that generates a Web-based representation of an IC
design. The Watt Watcher World Wide Web option (W5) allows designers using
any Web browser to traverse the design hierarchy, view the complete IC
power budget, the number and type of clocks in the design and estimated
area. W5 is available with Watt Watcher version 2.4.1.

The company also plans to demonstrate Peak Watcher, a tool that identifies
and analyzes peak power consumption of designs at the register-transfer
level. Using the company's Watt Watcher library format, the Unix software
can analyze ICs with up to five million or more transistors in hours.

PeakWatcher includes support for difficult-to-handle elements of the
design including memories, I/Os, and virtual components. Priced under $40,000,
PeakWatcher will be available in September.

SynaptiCAD (Blacksburg, VA) will release VeriLogger Pro, a Verilog
simulator with an interactive debugging environment (see Fig 3 ).
The software is an integration of Wellspring Solution's VeriWell IEEE 1364-compliant
Verilog simulator with SynaptiCAD's Waveformer Pro waveform viewing environment
along with additional debug and editing features.

Fig. 3 . SynaptiCAD's VeriLogger Pro integrates
a Verilog simulator with a waveform viewer to create
an interactive debug environment.

VeriLogger Pro supports the IEEE 1364 standard, including all RTL, behavioral,
and synthesizable constructs. The waveform viewer includes advanced timing-diagram
editing features for editing and documenting the waveforms. The software
is expected to ship in August, priced at $1,500 for the Windows 95/NT version
and $3,000 for Unix.

The Verilog-XL Desktop simulator will be exhibited by Cadence (San Jose,
CA). Priced from $12,000, the simulator is a lower-cost version of the
company's Verilog-XL Turbo simulator (see Fig. 4 ). Offered initially
for Windows NT, the simulator verifies the functional building blocks of
complex ASICs and systems-on-a-chip. It supports blocks of up to 20,000
gates and 2,000 lines of RTL code.

Fig. 4 . A lower-cost version of Verilog-XL, the Verilog-XL Desktop
simulator from Cadence functionally verifies complex ASICs with blocks of up to
20,000 gates and 2,000 lines of RTL code.

Frontier Design (Danville, CA) will introduce its algorithm-to-register-transfer
(A | RT) tools, which automate the conversion of C-based floating-point
algorithms to fixed-point synthesizable VHDL or Verilog descriptions. The
software targets designs that are too specialized or complex to be implemented
in general-purpose processor cores.

A | RT Library provides a library of fixed-point data representations
and operators so floating-point algorithms can be converted to fixed-point
representations. A | RT Builder automatically converts these fixed-point
C-algorithms to Verilog or VHDL. Pricing for A | RT Builder, which includes
the library, is $20,000. When purchased separately, the library costs $1,000.
A | RT Builder will be available in September for Unix platforms.