PLD tool enhances static-timing analysis

PLD tool enhances
static-timing analysis

Version 5.1 of the ispDS+ HDL Synthesis-Optimized Logic Fitter, a programmable-logic
design tool, features a variety of enhancements. The software's static-timing
analyzer includes path enumeration options, timing report generation, and
easier access to reports. The Explore Tool feature provides greater user
control over design implementation.

Version 5.1 adds support for third-party toolsets, including Viewlogic's
Workview Office, Minc's Synario, and Synplicity's Synplify. Other features
include support for the company's ispLSI 3320 and ispLSI 3448 PLDs, BGA
packaging, and libraries from Aldec, VeriBest, and Quad Systems. (PC version,
$1,295–available now.)

Lattice Semiconductor
Hillsboro, OR
Tim Schnettler 503-681-0118
Fax 503-681-3037
http://www.latticesemi.com