Programmable-logic vendors offer
tools to try their chips

By RODNEY MYRVAAGNES
Associate Editor

Programmable logic has benefited from the availability of advanced foundry processes to pack million-gate FPGAs and thousand-macrocell CPLDs. Devices suggested for new designs by their manufacturers are collected here (see table below).

The most recent introductions were covered in more detail recently (see Electronic Products , Nov. 1998, p. 41). Many of the makers of large-scale programmable logic have branched out in recent years, with Xilinx, the originator of FPGAs, introducing a CPLD line, and Vantis branching into FPGAs. One company, Altera, has even combined the two in its Apex 20K family.

Designers considering programmable logic for the first time may look for a way to test an idea without investing in a full-scale EDA suite, such as those covered recently (see Electronic Products , January, p. 34). It may be possible to try out a vendor's products with proprietary tools that the vendor supplies.

Chip-vendor tools

Actel (Sunnyvale, CA) offers the DeskTop tool suite at several price levels. The first-level suite includes Veribest Design View schematic and VHDL data entry.

Other functions include the Veribest design manager; a VHDL simulator for behavioral, functional, and gate-level simulation; and test-bench generation. It also includes Synplicity Synplify-Lite synthesis as well as Actel Designer-Lite place-and-route, logic analyzer, and timing analysis. Programming software is included in all versions. DeskTop is available free for one year, with one year of updates and technical support costing $995.

The second level, DeskTop with Verilog, adds Verilog entry and outlook, and costs $1,995 including one year of updates and support. Levels one and two are limited to 50,000-gate designs. The third level, Desktop Pro, adds VHDL or Verilog, and costs $3,495, including the first year of support. It has no size limitations.

Actel also offers a logic analyzer, called Actel Silicon Explorer, that probes the internal nodes of company chips, displaying waveforms on screen and producing BCE data files. A version for oscilloscopes costs $495. The PC version costs $1,295, including software and probe hardware.

Altera (San Jose, CA) has changed its software business to a pure subscription model. A flat $2,000 annual fee entitles the subscriber to the latest version of Max+Plus II and the soon-to-come Quartus, as well as maintenance. If a customer chooses not to renew, the customer can continue to use the existing tools and licenses without support.

Max+Plus II accepts VHDL, Verilog, schematic capture, entry of megafunctions, and the LPMModules, as well as Altera HDL and waveforms. Output can be selected for any of the company's programmable products. The software can exchange netlists with other tools in EDIF, VHDL, or Verilog formats.

Quartus software is designed for multi-million-gate designs. To this end, it will support multiprocessor compilation, block-level editing, workgroup computing, and expanded megafunctions. Megafunctions will include a PCI Master/Target for $14,995. A PCI development kit includes a Flex 10KE device, a prototype board, and software drivers for $4,995.

Atmel (San Jose, CA) offers two packages: Atmel-WinCUPL, distributed free, enables CUPL entry only for small PLDs; the other, Atmel-Synario, supports all the company's devices, both proprietary and Jedec.

Atmel-Synario combines schematic and behavioral entry in a Windows environment. It supports both functional and timing simulation. A design manager allows the user to move quickly between designs without getting files mixed, so alternative solutions to a problem may be tried and compared. The suite operates under Windows 95/NT and costs $895.

Warp2 software, from Cypress Semiconductor (San Jose, CA), accepts input in either VHDL or Verilog, and synthesizes output for any Cypress CPLD, as well as a variety of simple PLDs. Other features include context-sensitive color-coded HDL editors, a graphical editor for finite-state machines and a timing simulator from Aldec.

The synthesis tool searches the input for arithmetic and datapath operators, and replaces them with hand-crafted library circuits where possible. The user can retarget the output to any other supported device at a keystroke. The program sells for $99.

Lucent Technologies (Allentown, PA) offers the ORCA Foundry Designers Series, a package that combines the ORCA Foundry development system with the ViewLogic WorkView Office suite. The Foundry includes Scuba, a macrocell compiler; Epic, an interactive design editor; timing-driven place-and-route facilities; and static timing, along with VHDL and Verilog simulation libraries.

WorkView Office includes ViewDraw, a schematic-capture tool, FPGA Express for HDL synthesis, Intelliflow, a design and project manager, and ViewSim, a gate-level simulator. Three configurations are available, called Silver, Gold, and Platinum.

Silver supports ORCA 2C-A, 2T-A, and Series 3 devices up to 30,000 gates. It costs $300. Gold adds the ViewLogic Speedwave VHDL simulator. It costs $1,695. Platinum provides access to all ORCA FPGAs up to and including the OR3L225, for $5,995.

The ispExpert package from Lattice Semiconductor (Hillsboro, OR) accepts EDIF input from all third-party design-entry tools. It performs logic optimization, place and route, debug, and timing analysis, and outputs all standard formats to additional third-party tools. Other features include the ispAnalyzer silicon debug tool, Explore Tool compiler optimizer, and the Physical Viewer resource usage analysis tool.

IspExpert runs on Windows platforms and Unix workstations, and is priced from $995. A six-month starter version runs on Windows 95/98/NT only and is available free.

Philips Semiconductors (Sunnyvale, CA) offers two packages, both for Windows 95/98/NT. XPLA Designer XL, a free introductory program, accepts input in the proprietary Philips Hardware Description Language (PHDL) only. It includes an ac and functional simulation capability. XPLA Professional accepts VHDL, Verilog, and schematic input in addition to PHDL. It costs $245.

QuickLogic (Santa Clara, CA) offers both the entry-level Quick Tools-PC Plus and the QuickWorks suite. QuickTools includes schematic-design entry via an extensive set of macrofunctions, place and route, static timing analysis, and interfaces to third-party synthesis and simulation. For the PC, QuickTools is $495; for workstations it is $1,995. In addition, an OEM version of the Veribest simulator is available for $995.

QuickWorks provides a complete pASIC FPGA software solution from design entry, to logic synthesis, to place and route, to timing analysis and simulation. QuickWorks combines VHDL, Verilog, schematic, and mixed-mode entry with fast and efficient HDL synthesis provided by the integrated Synplicity Synplify-Lite tool.

The synthesis algorithms are specifically tuned to take advantage of the pASIC architecture, resulting in synthesized designs that typically require much smaller gate counts and run significantly faster than if they were implemented using software and devices from other FPGA vendors. A comprehensive Verilog or graphical simulation environment is also integrated with the Simucad Silos III simulator.

Direct correlation between simulation timing waveforms and Verilog source code provides a debug environment, a new capability for any FPGA tool suite. Quickworks costs $2,995 for a single license, and a 30-day evaluation copy can be downloaded free.

Design-Direct software, currently in beta from Vantis (Sunnyvale, CA), will over time replace MACHLX and the Minc fitters in third-party tools. It features ABEL-HDL and schematic capture, and accepts EDIF files from third-party tools.

The Base package offers functional simulation with ABEL test vectors, an optimized fitter for HDL flows, automatic fitting for all MACH and PAL devices, static timing analysis, a CPLD constraints editor, and netlist read/write capability. For third-party simulators, output files can be generated in EDIF, Verilog, SDF, and VITAL-compliant VHDL.

Also included, MACHPRO provides for in-system programming of MACH devices. The base system can be downloaded free from the company's Web site. It runs on Windows 95/98/NT, Solaris, and HP-UX.

The Vista system adds synthesis, source simulation, and timing simulation to the Base system. Its simulation facilities include Exemplar and ModelTech. It runs on Windows 95/98/NT-based computers and costs $1,495 for a single permanent license.

Xilinx (San Jose, CA) offers both Foundation, a fully integrated Windows-based tool suite, and Alliance, a back-end place-and-route tool that accepts input from third-party tool suites. Foundation Series tools use standard HDLs, including VHDL and Verilog, and support a broad range of Xilinx FPGAs and CPLDs. The software provides access to synthesis, schematic entry, gate-level simulation, and implementation tools. Prices range from $95 to $4,995.

The Alliance series supports all Xilinx parts, and is available for workstations as well as PCs. Depending on devices supported as well as the platform, the series ranges from $95 to $5,995.

FPGA Table Continued

*Actel has agreed to take over marketing GateField FPGAs, but the exact nature of the offerings was not ready
for disclosure at press time, so there are no GateField parts in the table.