Application Note 7534 July 2004 A New PSPICE Electro-Thermal Subcircuit For Power MOSFETs Alain Laprade, Scott Pearson, Stan Benczkowski, Gary Dolny, Frank Wheatley Abstract An empirical self-heating SPICE MOSFET model which accurately portrays the verti- cal DMOS power MOSFET electrical and thermal responses is presented. This macro-model implementation is the culmination of years of evolution in MOSFET modeling. This new version brings together the thermal and the electrical models of a VDMOS MOSFET. The existing electrical model [2,3] is highly accurate and is recog- nized in the industry. The sequence of the model calibration procedure using para- metric data is described.
1 July 2004 Rev. A, July 2004©2004 Fairchild Semiconductor Corporation Abstract An empirical self-heating SPICE MOSFET model which accurately portrays the verti- cal DMOS power MOSFET electrical and thermal responses is presented. This macro-model implementation is the culmination of years of evolution in MOSFET modeling. This new version brings together the thermal and the electrical models of a VDMOS MOSFET. The existing electrical model [2,3] is highly accurate and is recog- nized in the industry. The sequence of the model calibration procedure using para- metric data is described. Simulation response of the new self-heating MOSFET model track the dynamic thermal response and is independent of SPICE's global tem- perature definition. 1. Introduction Many power MOSFET models available today are based on an ideal lateral MOSFET device. They offer poor correlation between simulated and actual circuit performance in several areas. They have low and high current inaccuracies that could mislead power circuit designers. This situation is further complicated by the dynamic perfor- mance of the models. The ideal low power SPICE level-1 NMOS MOSFET model does not account for the nonlinear capacitive characteristics Ciss, Coss, Crss of a power MOSFET. Higher level SPICE MOSFET models may be used to implement the non-linear capacitance with mixed results. The need for this higher level modeling accuracy becomes apparent in high frequency applications where gate charge losses as a proportion of overall losses become significant. The inherent inaccuracies of modeling a power VDMOS with the SPICE MOSFET model dictated the need for an alternative approach; a macro-model. A macro-model such as the one defined by Wheatley and Hepp [1] can address the short comings of the ideal low power SPICE MOSFET model. Highly accurate results are possible by surrounding a temperature independent gain block (implemented using three level-1 MOSFET models ) with resistive, capacitive, inductive and other SPICE circuit elements. Application Note 7534 A New PSPICE Electro-Thermal Subcircuit For Power MOSFETs Alain Laprade, Scott Pearson, Stan Benczkowski, Gary Dolny, Frank Wheatley July 2004 2 Rev. A, July 2004©2004 Fairchild Semiconductor Corporation It is possible to develop a model from parametric measurements in a single iteration. The model extraction procedure from parametric data must follow a given sequence. Many of the changes to the model affect different behaviour. Failure to follow this sequence will result in repeated model calibration iterations. The MOSFET model reference on which this work is based has been explained in [1, 2, 3, 10]. The reader is encouraged to refer to these references for a full understand- ing of the MOSFET model parameters herein referenced. Use of the model, once extracted is not discussed here, but reference [10] addresses the use. Recent works [8, 9] have demonstrated methods of circumventing the SPICE global temperature definition, providing a means of using the device's own junction tempera- ture as a self-heating feedback mechanism. The model developed in [8] has limitations involving proprietary algorithms, rendering the method of limited interest. Model implementation is convoluted, involving a MOS- FET analog behavioral model (ABM) implementation whose operating characteristics are dependent on a SPICE level-3 NMOS MOSFET. As a result, both the switching circuit and the load must be duplicated for the model to function. The implementation in [9] does not model the drain-source avalanche property of a MOSFET. Neither [8] nor [9] attempt to model the temperature characteristics of the intrinsic body diode. Introduced self-heating modeling concepts are non-proprietary and may be adapted to other MOSFET models. 2. Self-Heating SPICE MOSFET Model The self-heating macro-model in Figure 1 is the evolution of years of work and improvements from numerous authors [1-7]. A significant advantage of this model is that knowledge of device physics or process details are not necessary to implement the parametric data within the model. 3 Rev. A, July 2004©2004 Fairchild Semiconductor Corporation Figure 1. Self-heating MOSFET macro-model independent of global temperature definition Parametric data for several temperature points are used for model calibration result- ing in a macro-model which provides representative simulation data for any rated operating junction temperature. Temperature dependent model parameters respond in closed loop form to the junc- tion temperature information provided by node Tj. Performance is independent of SPICE's global temperature definition listed as .TEMP and temperature option TNOM, circumventing the level-NMOS model primitive temperature limitation. All MOSFET operating losses are inclusive in the current source G_Pdiss representing instantaneous power dissipation to the thermal model. Multiple MOSFETs may be simulated at different and variable junction temperatures. Each MOSFET may be connected to a heat sink model via note Tcase. The heat sink model may be device specific, so heat sink optimization becomes possible. Current source G_Pdiss is referenced to the simulation ground reference, permitting use of the model in bridge topologies. An example of a symbol representation of the self-heating MOSFET model is shown in Figure 2. Symbol files for OrCAD's two circuit entry tools “PSPICE Schematic” and “OrCAD Capture” may be downloaded from wwww.fairchildsemi.com. Recom- mended symbol implementation is to designate the pinout attribute for Tj as optional (ERC = DON'T CARE, Float=UniqueNet). Tj is the representation of the device jun- tion temperature. It may be used as a monitoring point, or it may be connected to a defined voltage source to override the self-heating feature. Tcase must be connected to a heat sink model. Treatment of connections to the model's gate, drain, and sour- rce terminals are no different than those of the standard MOSFET model. + – DRAIN 2 LDRAIN RLDRAIN DBREAK DBODY DPLCAP 5 10 5 51 + – + – + – + – + – + – 6 8 6 8 5 8 51 RSLC2 ESG ESLC G_RDRAIN EBREAK MWEAK MMED MSTRO CIN G_RSOURCE LSOURCE RLSOURCE SOURCE 3 EVTEMP RGATE LGATE RLGATE GATE 1 CA CB S1A S2A S1B S2B EGS EDS 11 50 16 21 6 209 8 7 14 1513 8 14 13 13 12 EVTHRES G_RSLC1 CTHERM1RTHERM1 CTHERM6RTHERM6 CTHERM5RTHERM5 CTHERM2RTHERM2 CTHERM3RTHERM3 CTHERM4RTHERM4 G_PDISS 0 Tj Tcase 106 105 104 103 102 32 31 – + EDBODY 30 G_RDBODY G_RDBREAK RDBODY 4 Rev. A, July 2004©2004 Fairchild Semiconductor Corporation Figure 2 Self-heating MOSFET SPICE symbol 3. Self-Heating Model Implementation Ability to describe the value of a resistor and its temperature coefficients as a behav- ioral model referenced to a voltage node is necessary to express dependence on junction temperature. PSPICE resistor ABMs do not permit voltage node references. Dynamic temperature dependence of the MOSFET's resistive element (expressed as separate lumped elements) and of the diode's resistive component cannot be imple- mented without a resistor ABM. This limitation is overcome with a voltage-controlled current source ABM expression (Figure 3). By using the nodes of the current source for voltage control, resistor behaviour may be expressed as I = V/R(Tj). The resistance R(Tj) is replaced by a behavioral model expression dependent on the voltage node Tj representation of junction temperature. This voltage-controlled current source ABM model was used to implement voltage dependent expressions of RDRAIN, RSOURCE, and RSLC1. Figure 3. Implementing a voltage dependent ABM resistor model Temperature dependent resistive elements of diodes DBODY and DBREAK were separated from the diode model, and expressed as voltage-controlled current source ABM models G_RDBODY and G_RDBREAK. A very large value resistor RDBODY was added to improve convergence. EDBODY is added in series with DBODY to incorporate the temperature dependency of the intrinsic body diode forward conduction drop. Junction temperature information is implemented by the inclusion of the MOSFET's thermal network ZJC and current source G_PDISS. The thermal network parameters are supplied in Fairchild Semiconductor data sheets. G_PDISS calculates the MOS- FET instantaneous operating loss, and expresses the result in the form of a current. This is a circuit form implementation of the junction temperature from expression (1) I=V/R(Tj ) + – I + – 5 Rev. A, July 2004©2004 Fairchild Semiconductor Corporation (1) where Tj = junction temperature, Pdissipation = instantaneous power loss, ZJC = ther- mal impedance junction-to-case and Tcase = case temperature. The unite conversion for the electrical analog ofthe thermal system is listed in Table 1. Table 1 Electrical/thermal analogy 4. Parameter Extraction Methodology The sequence of the parameter extraction procedure is very important since many of the changes to the library affect differnt behavior. For instance, changing parameters in the transfer curve affect the saturation curves. The remcommended methodology is show below. 1. The transfer curve 2. The saturation curve 3. The body diode forward conduction 4. Breakdown voltage 5. Trr 6. Capacitance (Crss, Coss, Ciss) 7. Gate charge 8. Temperature coefficients 9. Thermal model Extraction is achieved more rapidly if data is plotted log-log, semilog, versus t, etc. First extraction may take days. It becomes a rapidly learned rocess with repeated usage. 4.1. Transfer Curve Three level-1 MOSFET transistors are used to model the gain block for the full current range from the sub-threshold region through high current. The three transistor mod- els are MweakMOD, MmedMOD and MstroMOD. The parameters VTO and KP of each transistor are used for alignment of the model with measured data. .MODEL MmedMOD NMOS (VTO=3.3 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.36 T_ABS=25) .MODEL MstroMOD NMOS (VTO=4.0 KP=275 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) caseJCndissipatioj TZPT += I Electrical Thermal Ohm o C/Watt Farad Joules/o C Amp Watt Volt o C 6 Rev. A, July 2004©2004 Fairchild Semiconductor Corporation .MODEL MweakMOD NMOS (VTO=2.72 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13.6 RS=0.1 T_ABS=25) Source resistance (G_Rsource) is added to lower the gain at high currents. It is also a contributing element to the device rDS(ON). Plotting the square root of IDS versus VGS results in a linear curve instead of a quadratic curve, thus improving the visual resolution of the daa at the higher current range. G_Rsource 8 7 VALUE={V(8,7)/(2.5e-3*(1+5e-3*(V(th+)-25)+1e-6*pwr((V(th+)- 25),2)))} 4.2. Saturation Curves Several gate biases should be used to model the saturation curves. For instance, to model a standard gate device use VGS=10V, 5V and 3.5V. G_Rdrain is used to fit the model in the linear region. Increasing G_Rdrain will decrease the current of the satu- ration curves. Next, the space charge limiting effect is modeled using ESLC. The muliplier X in ESLC (1e-6*X, the exponent of the power statement) is adjusted. Low- ering X will round off the curves at high currents. If two saturation curves (for instance at Vgs=10V and Vgs=5V) do not match in the linear region, it may be necessary to readjust KP of the strong transistor MstroMOD. Modeling between transfer and satu- ration curves will then need to be repeated until both curves fit the data. G_Rdrain 50 16 VALUE={V(50,16)/(1e-4* (1+5.5e-2*(v(th+)-25)+3.2e-4*PWR((v(th+)- 25),2)))} ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51))) *(PWR(V(5,51)/(1e-6*300),10)))} 4.3. Body Diode Forward Voltage Match diode curve data at low currents by adjusting parameters IS and N in Dbody- MOD. With the forwardvoltage plotted on a log scale, N will adjust the slope and IS will shift the curve left or right. .MODEL DbodyMOD D (IS=2.4e-11 N-1.04 CJO-4.35e-9 M=0.54 TT=1.0e-9 XTI=3.9 T_ABS=25) The high current region is modeled on the linear scale. G_Rdbody is used to match diode curve data at high currents by adding series resistance, thus lowering the curve. G_Rdbody 7 31 VALUE={V(7,31)/(1.65e-3* (1+2.7e-3*(V(TH+)-25)+2e- 7*PWR((V(TH+)-25),2)))} IKF can be used to smooth the transition region between low currents and high cur- 7 Rev. A, July 2004©2004 Fairchild Semiconductor Corporation rents. After changing IKF, it is often necessary to readjust G_Rdbody. .MODEL DbodyMOD D (IS=2.4e-11 N=1.04 CJO=4.35e-9 M=0.54 TT=1.0e-9 XTI=3.9 IKF=100 T_ABS=25) 4.4. Breakdown Voltage Low current breakdown is modeled with Ebreak. Ebreak 11 32 VALUE={69.3*(1+9.5e-4* (V(TH+)-25)+1e-7*PWR((V(TH=)-25),2)))} High current breakdown is modeled with G_Rdbreak. G_Rdbreak 32 7 VALUE={v(32,7)/(7.0e-2* (1+5e-4*(V(TH+)-25)+1e-7* PWR((V(TH+)-25),2)))} 4.5. Trr Intrinsic body diode reverse recovery is modeled at 100A/µS and the maximum rated DC current. Parameter TT of the body diode DbodyMOD is used to match the mod- eled Ta to the mearsured Ta. .MODEL DbodyMOD D (IS=2.4e-11 N=1.04 CJO=4.35e-9 M=0.54 TT=1.0e-9 XTI=3.9 T_ABS=25) 4.6. Capacitance Capacitance is moedled for drain-to-source voltages of 0.1V to the breakdown volt- age. Crss is modeled first, setting CJO and M of DplcapMOD. CJO will adjust the level of the capacitance curve while M will adjust the slope. Next Coss is modeled with CJO and M of DbodyMOD. This is done in a similar manner to Crss. Finally input capacitance Ciss is adjusted by setting Cin of the model. .MODEL DplcapMOD D (CJO=1.7e-9 IS=1e-30 N=10 M=0.47) .MODEL DplcapMOD D (IS=2.4e-11 N=1.04 CJO=4.35e-9 M=0.54 TT=1.0e-9 XTI=3.9 T_ABS=25) Cin 6 8 6.1e-9 4.7. Gate Charge Modeling of the gate charge curve is a four step process (Figure 4). First, adjust the slope through the most negative gate voltages by adjusting Ca. Next, adjust the slope breakpoint by adjusting S1A and S1B switch voltages (VON and VOFF) to account for 8 Rev. A, July 2004©2004 Fairchild Semiconductor Corporation the discontinuity between the two slopes at negative voltages. VON and VOFF of S1AMOD and S1BMOD should be the reverse of the one another (VON of S1AMOD should be VOFF of S1BMOD, and vice versa). Figure 4. Modeling gate charge Ca 12 8 1.5e-9 .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4) Third, switch voltages of S2A and S2B are adjusted to set the length of the plateau region. The voltage level of the plateau will be setup by the modeling done for the transfer curve and can not be adjusted at this point. S2AMOD and S2BMOD should be reverse of each other as stated above for S1AMOD and S1BMOD. Fourth, adjust the slope of the curve above the plateau by adjusting Cb. Ca and Cb should be nearly identical in value. Cb 15 14 1.5e-9 .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1) VON values for the switches S1A through S2B should be increasing in a positive direction. There should be a minimum of 0.5V separating each VON value. Reduc- tion of the separation below 0.5V can result in convergence errors. 4.8. Temperature Coefficients Repeat steps 4.1 through 4.4 at a low and high temperature (ex. -25o C and 125o C). For step 4.2 saturation curves, only one gate bias will be used in temperature coeffi- cient matching and should be the gate voltage that is used for rating rDS(ON). Temper- ature coefficients are not a factor for transient analyses (capacitance, Trr and gate charge). Transfer Curve: At high currents adjust the temperature parameters of Evtemp. At 9 Rev. A, July 2004©2004 Fairchild Semiconductor Corporation low currents adjust the temperature parameters of Evthres. The temperature coeffi- cients of G_Rsource may be used to fit the curve at high currents. The first parameter highlighted in each line below is a linear coefficient and the second is a square func- tion coefficent. Evtemp 20 6 VALUE={-2.5e-3*(V(TH+)-25) +1e-6*PWR((V(TH+)-25),2)} Evtemp 6 21 VALUE={-6.7e-3*(V(TH+)-25) -1.5e-5*PWR ((V(TH+)-25),2)} G_Rsource 8 7 VALUE={V(8,7)/(2.5e-3* (1+5e-3*(V(th+)-25)+1e-6*pwr((V(th+)- 25),2)))} Saturation Curves: First adjust the temperature parameters of G_Rdrain. Then model the temperature parameters of G_RSLC1. This models the space charge limit- ing effect over temperature. G_Rdrain 50 16 VALUE={V(50,16)/(1e-4* (1+5.5e-2*(v(th+)-25)+3.2e-4*pwr((v(th+)- 25),2)))} G_RSLC1 5 51 VALUE={V(5,51)/(1e-6* (1+1e-3*(v(th+)-25)+1e-5*pwr((v(th+)- 25),2)))} Body Diode Forward Voltage: At low currents the forward voltage is modeled with the temperature coefficients of EDbody. The last parameter in EDbody is used to limit Vf above 175oC. Thermal parameters of G_Rdbody are used to model the high current region. EDbody 31 30 VALUE={IF(V(TH+)<_1752c_-1.5e-32a_v28_th2b_29_2b_.032c_0.232529_7d_ g_rdbody="" value="" _28_12b_2.7e-32a_28_v28_th2b_29_-2529_2b_2e-="" _72a_pwr28_28_t28_th2b_29_-2529_2c_229_29_29_7d_="" breakdown="" _voltage3a_="" low="" current="" is="" modeled="" with="" thermal="" parameters="" of="" ebreak.="" g_rdbreak="" are="" used="" to="" model="" high="" current.="" _28_12b_5e-42a_28_v28_th2b_29_-2529_2b_1e-72a_pwr28_28_t28_th2b_29_-="" _2529_2c_229_29_29_="" ebreak="" the="" independently="" electrical="" model.="" components="" ctherm1="" through="" ctherm6="" and="" rtherm1="" rtherm6="" fit="" simulated="" impedance="" curve="" measured="" data.="" ensure="" a="" good="" _model2c_="" capacitors="" should="" be="" increasing="" in="" from="" ctherm6.="" resistors="" also="" rtherm6.="" rev.="" _a2c_="" july="" _2004c2a9_2004="" fairchild="" semiconductor="" corporation="" tj="" ctherm2="" ctherm3="" ctherm4="" ctherm5="" tcase="" rtherm2="" rtherm3="" rtherm4="" rtherm5="" simulation="" results="" simulaton="" parametric="" data="" mosfet="" fdp038an06a0="" plotted="" figures="" _42c_="" _52c_="" _62c_="" for="" gate="" _charge2c_="" _threshold2c_="" _rds28_on29_2c_="" conduction="" saturation="" voltage.="" excellent="" agreement="" exists.="" figure="" threshold="" voltage="" _conditions3a_="" id="250µA" temperature="" _28_="" o="" _c29_="" _vgs28_th29_="" fdp038an08a0="" standard="" self-heating="">
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