Agere Systems Tapes Out Next-Generation, 90-NM Mobile Solution Chip Using Cadence X Architecture
Agere Systems and Cadence Design Systems announced that Agere has completed design and implementation on a next-generation, 90-nanometer, mobile handset chipset using the Cadence X Architecture and successfully taped it out.
X Architecture Provides Significant Die-Size and Power Dissipation Reduction for Agere's Vision Mobile Handset Design
Agere Systems and Cadence Design Systems announced that Agere has completed design and implementation on a next-generation, 90-nanometer, mobile handset chipset using the Cadence X Architecture and successfully taped it out.
“Agere is impressed with the die-size reduction and reduced power dissipation resulting from the wirelength reduction achieved with the X Architecture,” said Craig Garen, vice president of mobility product development with Agere. “Our company has confirmed that the Cadence X Architecture has realized a wirelength reduction of more than nine meters approximately 30 percent versus previously used 'Manhattan' routing in the same technology. The ease with which the Cadence X Architecture integrated into our sign-off flow enabled us to meet our aggressive tape-out schedule.”
“TSMC is focused on enabling innovative solutions like the X Architecture for our customers,” said Ed Wan, senior director of TSMC's design services marketing. “We're pleased to see key customers like Agere reap the benefits of our collaboration with Cadence on the X Architecture.”
About the X Architecture
The X Architecture represents a new way of orienting a chip's microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle Manhattan routing. The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly less wirelength and fewer vias (the connectors between wiring layers).
Advertisement
