PLD-based video interfaces connect consumer electronics
There are several methods for integrating image and video data transfer functionality into portable devices
BY TAM DO
Altera
San Jose, CA
http://www.altera.com
The rapid proliferation of consumer video applications from portable media players and mobile phones to video game consoles requires a variety of interfaces and adapters that allow users to transfer video data to and from their computers and various gadgets.
One of the challenges designers face is how to best and most cost-effectively bridge the gap from source to sink for the varying high-speed video content. Common consumer video interfaces include IEEE 1394 (FireWire), USB 2.0, DVI, HDMI, and various wireless. This article shows how to use programmable logic devices (PLDs) to bridge, format, and route the different high-speed video content to a video display.
Video inputs
Today USB 2.0 is the mainstream high-speed video link between gadgets and computers. USB 2.0 uses NRZI coding and has a bandwidth of 480 Mbits/s (60 Mbytes/s). Digital cameras, set-top boxes, information appliances, MP3 players, personal digital assistants, game consoles, and 3-G cell phones each has one or two USB 2.0 interface ports.
The USB host can source power to external devices at up to 500 mA/5V at 5 m of cable and can support a maximum of 127 devices. Digital TV tuners are fitted with a USB module allowing users to plug it into their portable computer and watch television while on the road.
Standard-definition decoded video has a transfer data rate of up to 8 Mbits/s while high-definition decoded video needs up to 55 Mbits/s, well below the USB 2.0 speeds. A low-cost application-specific standard product (ASSP) host/device USB controller can be used as the physical (PHY) interface for video. The output parallel bus can be routed to a PLD for further data processing and, for additional integration, the USB MAC can be designed into the PLD.
The parallel video data can also be multiplexed to a final video decoder for display. The outputs of the USB 2.0 PHY chip can be easily connected to any I/O pins on the PLD. Most PLD I/O pins can be programmed to 3.3-, 2.5-, 1.8-, or 1.5-V LVTTL/LVCMOS.
IEEE 1394 (FireWire) uses full-duplex 8b/10b coding and can transfer data at up to 400 Mbits/s. The interface can run without host control, communicates peer-to-peer, has a maximum cable length of 4.5 m, and supports up to 63 devices. It specifies up to 1.25-A 12-V power for connected devices.
This interface is used primarily in digital video cameras. Similar to the USB 2.0, there are low-cost physical layer ASSPs available that can be used as the interface to PLDs that further enhances data processing.
Video outputs
Digital Visual Interface (DVI) and its sister technology, High Definition Multimedia Interface (HDMI) are both high-bandwidth digital interfaces for standard-definition (SD) and high definition (HD) video. The DVI interface targets at personal computers and peripherals such as monitors and projectors, while HDMI targets the digital entertainment market.
Both DVI and HDMI use transition minimized differential signaling (TMDS) channels with 8B/10B encoding. Type A HDMI is backward-compatible with the single-link DVI-D for digital only. This means that a DVI output can drive an HDMI monitor, or vice versa, by means of a suitable adapter, but the audio and remote control features of HDMI will not be available.
Type B HDMI is similarly backward compatible with dual-link DVI. An additional security feature, high bandwidth digital content protection (HDCP) protocol, is used to prevent the end user from viewing or copying restricted contents. Most HDMI ports support HDCP, while DVI ports usually do not.
Various off-the-shelf DVI and HDMI PHY chips can be interfaced directly to a PLD. Image processing and enhancement, such as deinterlacing, color space converting, scaling, 2D filtering, alpha blending, chroma resampling, and video line buffer compilers are usually provided by PLDs. These are perfect applications for today's PLDs that feature large logic cells, DSP blocks, and memory.
Most consumer semiconductors provide an I2 C interface for control and configuration. There are also many reference designs available for download and reuse including one at www.altera.com/end-markets/refdesigns. The Altera I2 C controller is available in VHDL optimized for the Altera's PLD families. In the design, all of the register addresses are defined as constants in the VHDL source files and can be easily customized by the designer. The memory base address register (MBASE) address is defined as generic and can be easily changed or customized. The design provides an output indicator signal on a pin that can be used by the microcontroller as an indicator when the I2 C data transfer is complete.
System application example
Most PLDs are designed to accept digital video sources with different formats and protocols. To display these video streams via an off-the-shelf digital encoder (DENC) chip, PLDs execute a format conversion of the input video data into a 10-bit CCIR 656 standard parallel video bus. These buses can be selected or multiplexed out into the DENC.
Figure 1 shows a PLD application block diagram linking these digital video sources to a video display. A typical PLD with a high I/O pin count can easily accommodate parallel video data from the PHY chips.
Fig. 1 Digital video sources can be linked to a display with the aid of a PLD.
The different data buses from USB, IEEE 1394, etc. are initially routed into the general purpose I/O pins. The second design step is formatting the parallel video data into a generic video bus, thus allowing multiplexing or selection for display. The I2 C reference design is used to control the configuration of both the PLD and the on-board ASSP.
Figure 2 shows an overall system block diagram including the video PHY chips linking into the PLD. The output of the PLD produces a CCIR 656 video format data bus into an off-the-shelf video encoder. All controls to the PLD and standard chips are accomplished by using the I2 C reference design.
Fig. 2. Video PHY chips link to a PLD, which then produces a CCIR 656 video format at the data bus.
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