Low-power 44-Gbit/s CDR chip is built in CMOS

Low-power 44-Gbit/s CDR chip is built in CMOS

Fujitsu Laboratories (Sunnyvale, CA) has developed the industry’s first CMOS IC to perform clock and data recovery (CDR) at 40 to 44 Gbits/s, enabling future implementation of high-speed optical SerDes modules. A paper delivered at the annual International Solid State Circuits Conference (ISSCC) in San Francisco described the prototype chip as demultiplexing data to 16 x 2.5 Gbits/s and complying with the ITU G.8251 jitter-tolerance mask standard.

A prototype CDR chip reaches speeds of 44 Gbits/s.

The IC dissipates 0.9 W at 40 Gbits/s, less than one-third the power of similar devices implemented in SiGe, BiCMOS, or other compound semiconductor technologies. It uses a novel 3X oversampling architecture and its input data is sampled using a 24-phase 10-GHz distributed VCO. The 0.8 x 1.8-mm2 1.2-V chip was made using a 90-nm process. Samples of a commercial version are expected in eight months. For more information, visit http://www.fujitsu.com/us.

—Jim Harrison