Tool gives SoC/ASIC/FPGA timing closure

EnVision TCV is said to be the only complete software solution for timing closure verification and includes the Meridian module for clock domain crossing and PureTime for timing exception verification. It covers two sources of errors not tackled by typical functional verification

The tool verifies that data traversing asynchronous clock domains on ASIC, SOC or FPGA devices is received reliably and removes the risk of errors in Synopsys Design Constraint (SDC) timing exceptions. It will analyze multi cycle paths and provide full sequential analysis. ($97,000-available now.)

Real Intent , Sunnyvale , CA
Sales 408-830-0700
www.realintent.com