FPGA design tool ups chip performance

Version 7.0 of the ispLEVER FPGA design tool package for Lattice devices features optimized logic synthesis, map, and place-and-route algorithms that are said to increase chip performance by at least 12%. The package also has a second-generation logic analysis/debug tool, a more accurate power calculator module, and enhancements to the embedded open source microprocessor design tools.

Nonvolatile 90-nm FPGA devices are supported and design compile times have been reduced by up to 70%, with an average improvement of 30%. The packages Reveal Logic Analyzer allows the user to define signals of interest for which it then inserts instrumentation (added FPGA test/monitoring circuitry) to improve system-level design debug. (From $895—available now.)

Lattice Semiconductor , Hillsboro , OR
Brian Kiernan 503-268-8739

http://www.latticesemi.com