FPGAs tackle low-power high-performance DSP apps

FPGAs tackle low-power high-performance DSP apps

Chips use 250-MHz DSP slices to deliver 4.06 GMACS/mW

The Spartan-3A XC3SD1800A and XC3SD3400A low-power DSP FPGAs feature a 50% static power savings, and a 70% savings in suspend mode, compared with standard devices, and are available in industrial temperature grades. They have 1.8- or 3.4-million system gates and deliver up to 4.06 GMACS/mW at 250 MHz.

The devices’ ability to perform signal-processing functions without consuming logic resources enables designers to meet their performance and cost goals with better power efficiency. Typical power dissipation of the 1.8-M-system-gate device is 149 to 407 mW. The slices that make up the dedicated DSP circuitry include dedicated 18 x 18 multipliers, an 18-bit pre-adder, and a 48-bit post-adder/accumulator.

The chips have 260 K or 373 Kbits of distributed RAM and 1.1 or 2.3 Mbits of block RAM and come in 484- or 676-ball chip-scale grid array packages. (Ea/25,000, industrial grade, 2008 pricing: XC3SD1800A-4LI, $34.80; XC3SD3400A-4LI, $50.00—available now.)

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