The HIT-Kit 3.72 high-voltage process design kit is based on Cadence version 5.1.41 and includes updated periphery cell libraries up to 50 V as well as the recently announced set of 20-V devices optimized for power management products and display drivers in battery-powered applications. In addition, the HIT-Kit offers unique design utilities such as the Safe Operating Area Check (SOAC) tool, automatic layout generators for high-voltage device and guard-ring generation and special layout verification utilities such as leakage check.
The kit also contains a complete set of fully silicon-qualified standard cells, periphery cells and general purpose analog cells such as comparators, op amps, and low-power ADCs and DACs. All I/O structures within the kit are silicon validated and meet the military ESD and JEDEC latchup standards with I/O pads designed to surpass up to 4-kV HBM and 250-mA latchup immunity. (Call company for pricing and availability.)
austriamicrosystems , Premstaetten , Austria
Sonja Pieber-Hascher 011-43-3136-500-5968
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