Cortex-A9 processors reach 8,000 DMIPS

The 32-bit Cortex-A9 MPCore multicore and Cortex-A9 single-core processor IPs deliver 2,000 to 8,000 aggregated DMIPS performance within tight power constraints. The IPs use a dynamic-length eight-stage-superscalar multi-issue pipeline with speculative out-of-order execution. They can execute up to four instructions per cycle while clocked at more than 1 GHz.

The processors are intended for mobile applications and feature a 250-mW basic power budget. They also feature an accelerator coherence port (ACP), an advanced bus interface unit for low latency in high-bandwidth devices, and multicore Trustzone technology with interrupt virtualization to enable hardware-based security. The processor is supported by the RealView Development Suite with advanced code generation tools. (Contact company for license information—available now.)

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