FPGA development tool affords power savings

The Libero chip design integrated development environment (IDE) v8.1 maximizes power efficiency with new power-driven layout and advanced power analysis. The tool is said to reduce dynamic power consumption by as much as 30%. The IDE supports IGLOO FPGAs and the company’s mixed-signal programmable system chip designs. Power reductions of 13% are typical.

Power-driven layout lowers dynamic power through the reduction of the capacitive loading of the nets. A cycle-accurate power analysis option allows designers to look at peak power per clock cycle as well as the average power for the entire simulation, and the switching analysis function identifies “hazards,” or spurious transitions, that contribute to higher power usage. ($2,495, free limited edition, one-year renewable licenses—available now.)

Actel , Mountain View , CA
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http://www.actel.com