FPGA design tool gets upgrade

ispLEVER 7.1 Lattice FPGA design tool suite features include a dedicated simultaneous switching output analyzer that allows designers to actively analyze and optimize I/O pin placement and output-switching characteristics to minimize noise and ground bounce. The suite delivers up to 30% faster design compile times and adds Synplicity’s Synplify Pro and Aldec’s Active-HDL as elements of the design flow.

The tool now supports Windows Vista and features numerous enhancements to Project Navigator, Interactive Synthesis Flow, and Design Planner modules. It runs with Windows, Linux, and Unix. (Windows version, from $895 — available now.)

Lattice Semiconductor , Hillsboro , OR
Brian Kiernan 503-268-8739

http://www.latticesemi.com