EDA News

Spicing up Spice

At its opening 2008 Technology Symposium, TSMC (www.tsmc.com) unveiled a comprehensive Spice Tool Qualification Program that drives its Design Service ecosystem partners to develop Spice simulators with greater accuracy and higher performance. Targeting TSMC’s 65-nm, 40-nm, and smaller-geometry process technologies, the program’s benefits include improved device model accuracy, enhanced simulation efficiency, and compatibility with qualified Spice simulators.

Qualifying 65 nm

Cadence Design Systems (www.cadence.com) announced the qualification of Cadence QRC Extraction and Virtuoso Passive Component Designer for the TSMC 65-nmr process design kit. Cadence QRC Extraction handles parasitic inductance and substrate extraction, while the Virtuoso Passive Component Designer tackles inductor synthesis, analysis, and modeling. The technologies were qualified as part of the new TSMC Electromagnetic Tool Qualification Program, which targets TSMC 90- and 65-nm process technologies. The program ensures greater electromagnetic accuracy for high-speed digital clock circuits and high-frequency mixed-signal RF design flows.

Lattice, Aldec alliance

Lattice Semiconductor (www.latticesemi.com) and Aldec (www.aldec.com) announced an agreement that will deliver the only OEM FPGA mixed-language simulator. Active-HDL Lattice Edition will be bundled with Lattice’s ispLEVER design tool suite, providing mixed-language simulation (VHDL, Verilog, and SystemVerilog), co-simulation with Simulink from The MathWorks and simulation support for Lattice-encrypted IP cores.