Media Alert – Rambus to Outline Mobile and Multicore Memory Challenges and Solutions at MemCon 2008
Los Altos, California, United States – 07/21/2008
Who: Rambus Inc. (Nasdaq: RMBS)
Where: Denali MemCon 2008
Hyatt Regency
5101 Great America Parkway
Santa Clara, CA
Booth #14
When: July 21-24, 2008
Join Rambus at MemCon 2008 for demos, displays, and presentations of our latest technology developments.
Rambus Presentations:
Wednesday, July 23, 10:30 AM PDT
Title: The Next Generation of Mobile Memory
Presented by: Judy Chen, Ph.D., Strategic Marketing Manger and Fredrick Ware, Technical Director at Rambus
Main Presentation Hall, Ballrooms E-H
Thursday, July 24, 9:45 AM PT
Title: Memory System Challenges in the MultiCore Era
Presented by: Steven Woo, Ph.D., Technical Director
Main Presentation Hall, Ballrooms E-H
Rambus Booth Demonstrations:
The Terabyte Bandwidth Initiative, featuring new memory signaling innovations that facilitate data rates of 16Gbps and a future memory architecture that can deliver an unprecedented terabyte per second (TB/s) of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC). Innovations include the industry’s first differential signaling for both data and command/address (C/A); FlexLink C/A, the industry’s first full-speed, point-to-point C/A link; and 32X Data Rate technology (32 data bits per input clock cycle).
The award-winning XDR memory architecture: a low-cost XDR system solution operating at 3.2Gbps data rate, on a two-layer printed circuit board. The test board shows a Rambus XDR PHY and memory controller interfacing to an XDR DRAM.
A PLAYSTATION®3 (PS3) Open Demo Board featuring XDR technology. The Rambus XDR memory interface and FlexIO processor bus enable an unprecedented aggregate bandwidth of over 90 gigabytes-per-second between the Cell Broadband Engine and supporting chips at the heart of the PS3.
TI DLP Open Demo Board: Rambus is showing an open TI DLP projector development board, highlighting Rambus XDR technology inside. The development board includes a 4.0Gbps, 16-bit XDR interface, an XDR Memory Controller (XMC), XDR memory cell interface (XIO), XDR DRAM, and the XDR Clock Generator (XCG). XDR has been adopted by TI for use in their DLP graphics engines, targeted at consumer projectors. TI DLP technology, included in Sharp projectors, is one of many consumer-level applications taking advantage of the XDR memory architecture.
For registration and additional information, please visit http://www.denali.com/memcon.
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