IJTAG is becoming a standard design validation interface
BY AL CROUCH
ASSET InterTech
Richardson, TX
http://www.asset-intertech.com
Since its ratification in the early 1990s, the IEEE 1149.1 Boundary Scan (JTAG) specification has shown that a well-thought-out standard can be resilient, adaptive, and quite useful in applications that were never considered during its development. Still a workhorse in non-invasive structural testing, boundary scan has expanded its role significantly over the years, becoming the base technology for several tag-along standards such as IEEE 1149.6 for high-speed serial bus testing and IEEE 1532 for in-system programming.
The latest, and perhaps most significant, application for boundary scan is emerging now as semiconductor vendors and system manufacturers embed functionality into chips in what is becoming known as embedded instrumentation. This application can be defined as logic designed into semiconductors and used for design validation, test, debug, yield analysis, and other activities such as monitoring and controlling what’s going on inside chips — as well as on boards and whole systems.
Instrumentation in the chip
Intel’s Interconnect Built-In Self-Test (IBIST) is a prime example of embedded instrumentation. IBIST validates and tests high-speed serial buses like PCI Express that can’t be tested with physical probes and external instruments. Logic BIST, memory BIST, scan compression architectures, and embedded-core wrappers are also commonly provided as “inside-the-chip” test functions that fall into this “instrumentation” category.
Very fast processors, interconnects, and interfaces along with exceedingly complex packaging technologies that incorporate several processing cores, multiple stacked dies, and other features that make physical access to logic and pins impossible are some of the trends that are thrusting embedded instrumentation to the forefront. Embedded instrumentation is becoming the only way to perform certain tests because there is no physical access for a probe.
Boundary scan’s test access port (TAP), the TAP controller, and certain elements of the 1149.1 boundary scan standard are being used as the access method for embedded instrumentation. Ultimately, open tools and a unified tools platform are needed to take full advantage of embedded instrumentation.
These tools would automate the use and access of instruments, and collect and analyze the data they generate. To ensure the openness of a tools environment it must be based on industry standards. This is where the Internal JTAG (IJTAG) preliminary standard comes in.
What’s IJTAG?
At least initially, JTAG, which is synonymous with boundary scan, has been appropriated as the base infrastructure for the still preliminary IJTAG standard (IEEE P1687). The goal of the P1687 IJTAG working group is to develop a standard way of connecting, accessing, analyzing, and describing embedded instrumentation intellectual property (IP) regardless of where it comes from — a chip supplier, a third party, an EDA tool, or an in-house design group.
The IJTAG architecture, which is still in the conceptual stage, delineates three basic partitions: the boundary scan/JTAG infrastructure as seen from the circuit board, a transitional gateway zone which interfaces the 1149.1 infrastructure, and the instrumentation IP.
Fig. 1. The diagram shows the three zones or partitions that comprise the IJTAG architecture.
The transitional gateway elements in the middle partition act as bridges between instruments and their interconnecting serial scan data paths within a chip and the JTAG’s TAP controller which provides access from the circuit board level. They enable board-level access to embedded instruments directly from the boundary scan TAP.
The transitional partition in the IJTAG architecture conforms to the boundary scan standard, but includes several of its own instructions for accessing the instrument gateways themselves. These gateways decouple the transitional partition from the instrument zone so that the IEEE P1687 portion is not limited by compliance to the boundary scan standard.
In addition, a gateway can be an instrument in its own right, but it also must enable a hierarchical connection with another embedded instrument for which it acts as a gateway. This hierarchical gateway connection involves passing JTAG control and data signals and a local select function to subsequent instruments.
Besides including IJTAG-compliant instruments, the instrumentation zone could feature one or more IJTAG Alternate Controller(s), which act as conversion elements and allow non-IJTAG instruments to reside alongside IJTAG instruments. An Alternate Controller can create control signals for just one instrument, groups of instruments, or signals that are global to the entire instrumentation partition.
Conceptually, the Alternate Controller can create control sequences that are not compliant with the boundary scan infrastructure but that may be required by complex instruments, such as sophisticated IEEE 1500 core wrappers that use non-1149.1 sequences, a clock other than the clock defined by the 1149.1 infrastructure, or a data path other than the boundary scan serial scan path.
Instrument architecture
Conceptually, embedded instruments can be configured in daisy-chain, star or a hierarchical arrangement. Each has its own inherent strengths and weaknesses.
Choosing one architecture over another involves tradeoffs at both the chip and board levels. For example, daisy-chaining together multiple instruments has advantages in terms of simplicity, command handling, and scheduling.
The architecture itself is simple since there is only one scan chain, and one command can activate all the instruments on the chain. However, a single failure on the daisy-chain can bring down all the instruments, access latencies can be extensive, and power consumption significant when many instruments are daisy-chained.
In contrast, a star configuration will have shorter latencies, since the scan path to each instrument will be shorter. This would reduce power consumption and a failure on one scan path would not jeopardize the operations of the other scan paths. A star architecture has less flexibility when it comes to concurrent instrumentation operation and greater complexity with regard to scheduling instrumentation functionality.
Arranging instruments in a hierarchical relationship can offer greater flexibility in scheduling tasks and the length of the scan path to instruments can be dynamically adjusted and latencies reduced. A failure on one path would not necessarily affect other scan paths. Of course, dynamically configured scan paths add to the complexity of the system. ■
For more on boundary scan, visit http://www2.electronicproducts.com/Test-Measurement.aspx.
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