Renesas Technology Receives Certification for New IP that Supports the PCI Express 2.0 High-speed Serial Inter

Renesas Technology Receives Certification for New IP that Supports the PCI Express 2.0 High-speed Serial Interface Standard

IP supporting the 65-nm process node allows 5Gbps data transfers and will be used in advanced semiconductor solutions for graphics, networking and data storage applications.

SAN JOSE, Calif. — December 16, 2008 — Renesas Technology America, Inc. today announced the development of a new logical- and physical-layer intellectual property (IP) conforming to PCI ExpressBase Specification Revision 2.0 (PCI Express 2.0 or PCIe 2.0), the latest version of the widely used serial interface standard. This IP allows data transfers at up to 5.0 gigabits per second (5Gbps) and supports the 65-nm semiconductor process node. Further, it was one of the first to receive Rev. 2.0 certification at Compliance Workshop #62 (September 8-12, 2008), sponsored by the standards body PCI-SIG. Microcontrollers, microprocessors and system-on-chip (SoC) devices incorporating this IP can make easy connections to other devices that support the PCI Express 2.0 standard.

Renesas plans to release the first products incorporating the new IP in 2009. Those devices will meet the needs of engineers designing graphics, storage and other products that must rapidly transfer large volumes of data. The company plans to eventually extend to process nodes even finer than 65 nm, and to provide enhanced functionality for key applications, such as an increased number of lanes. To facilitate development work by customers, system environment evaluations will be promoted, including the PCI-SIG Compliance Program.

Features of the certified PCI Express 2.0 IP

The new PCI Express 2.0 IP has three main features:

(1) Official certification for supporting the latest PCI Express standard, Rev. 2.0

PCI Express is a high-speed serial interface employing differential signaling. The maximum transfer speed of the latest Rev. 2.0 standard is 5.0Gbps, double that of the 2.5Gbps of the earlier Rev. 1.1 standard. The upgraded capability translates into high-speed data transfer at an effective rate of 500 megabytes (500MB) per second per lane. For this reason, more sophisticated and difficult design technology is required to realize circuits that can handle Rev. 2.0.

Renesas had previously developed and employed in products IP supporting Rev. 1.1. The company has applied the expertise gained over the development of its previous-generation IP Rev. 1.1 to develop the new IP supporting Rev. 2.0 at the 65 nm process node. This IP is among the first in the industry to receive Rev. 2.0 certification.

Microprocessor or SoC products incorporating this certified IP will enable developers to create high-speed systems capable of transferring large volumes of data very rapidly.

(2) Reduced power consumption

The new IP implements an up-configuration function that dynamically switches the transfer rate during operation. As specified in the PCI Express 2.0 standard, this function enables dynamic switching as follows:

When high-speed data transfer is required, multiple lanes can be used, with each operating at the maximum transfer speed of 5.0Gbps.

When the transfer volume is lower, priority is given to reducing power consumption. Only one lane operates at a transfer speed of 2.5Gbps, which is half the maximum rate.

The new Renesas IP achieves power consumption up to 50 percent less per Gbps than the company’s earlier IP, which supports Rev. 1.1. The combination of the existing power-management function and the new up-configuration function contribute to substantial decreases in overall system power consumption.

(3) Ability to select function options to suit specific applications

When the new IP is incorporated into products such as microcontrollers, microprocessors, or SoCs, customers will be able to select function options suitable for their target systems.

The main function options will include device attributes (root port/endpoint selection), maximum payload size, number of virtual channels, number of functions, on-chip buffer size, and number of lanes. By combining these options appropriately, customers will be able to realize an LSI product that is ideal for the system they are developing. ■