Design Challenges for an Ultra-Low-Jitter Clock Synthesizer
This application note presents a design idea for an ultra-low-jitter clock synthesizer. The target performance is < 100fs of edge-to-edge jitter at 2GHz. The discussion and simulation test results show that the target jitter proved harder to attain than originally anticipated. Component variables and tradeoffs are discussed for future development efforts.
This is a reference design for a low-jitter clock source for high-speed data converters. The goal is to achieve < 100fs of edge-to-edge jitter at frequencies up to 2GHz. For a 1GHz analog output frequency, this results in a jitter SNR of -20 × log(2 × π × f × tj) = -64dB.
Design Requirements:
The maximum intended frequency for this clock design is 2GHz. However, there are alternate VCOs (voltage-controlled oscillators) and prescalers available that can extend the frequency higher, each device producing differing results. This reference design, simulation tests, and results are focused on performance only at 2GHz output frequency.
Some high-speed converters use both edges of the clock signal for internal timing. Consequently, a critical design requirement is a 50% duty cycle. Additionally, the targeted output drive is 10dBm into 50Ω, or a 2VP-P differential.
Read the complete article at: http://www.maxim-ic.com/appnotes.cfm/an_pk/4336
Advertisement
