Mentor Graphics Unveils Advanced Low Power Features in its Olympus-SoC Place-and-Route Platform
WILSONVILLE, Ore., April 6, 2009 – Mentor Graphics Corporation (NASDAQ: MENT) today announced immediate availability of the Olympus-SoC platform with new features for low power IC implementation. The low power capabilities are targeted for advanced technology processes and take advantage of the Olympus-SoC production-proven design-for-variability architecture that natively optimizes for variations in design modes, process corners and manufacturing. Consequently, the Olympus-SoC customers are experiencing 2-3X faster design closure times, as well as a 30% power savings versus traditional solutions.
The Olympus-SoC low power solution includes a flexible architecture for automated multi-voltage design flow, and advanced techniques for power reduction in complex clock trees. It also includes concurrent optimization of leakage and dynamic power, timing and signal integrity across multi-corner multi-mode (MCMM) scenarios.
“Low power has become an imperative design metric for our advanced mobile computing requirements,” said Noboru Yokota, General Manager, Technology Development Division, Fujitsu Microelectronics Limited. “Since the Olympus-SoC platform is an integral part of our design closure system, we partnered with Mentor to incorporate advanced low power capabilities into our methodology. Advanced low power techniques, including multi-voltage, MCMM-CTS, clock tree restructuring, skew tuning and slew shaping, were evaluated—the results look impressive, with savings in overall power in addition to design closure at all modes and corners.”
Low Power Design Challenges
Multi-voltage design, a mainstream technique to reduce total power, is a complex, time-consuming task. This is because many blocks operating at different voltages, or intermittently shut off, increases the number of power states, which compounds the already complex MCMM problem. Incumbent place-and-route systems that do not have native MCMM capabilities are not able to efficiently handle the complexity of optimizing both power and timing concurrently. Additionally, because power consumption in the clock tree network is a significant portion of the total chip power, designers need power-aware clock tree synthesis (CTS) solutions that can deal with increasing wire resistance and resistance variability at smaller geometries. Finally, design sizes are increasing exponentially as more functionality is packed on a die, especially for mobile applications. Inability of incumbent tools to handle large design sizes forces designers to chop designs into manageable pieces, which complicates top-level chip assembly closure.
The Olympus-SoC Low Power Platform Delivers Comprehensive Power Management Capabilities
The Olympus-SoC place-and-route platform comprehensively handles the requirements of low-power design, while ensuring optimization of the overall solution without excessive design iterations, enabling engineers to rapidly deliver fully-optimized, power-efficient designs. The Olympus-SoC system includes the following key technologies to address low power challenges and deliver best quality of results:
Completely automated multi-voltage flow with support for Dynamic Voltage and Frequency Scaling (DVFS) to handle varying supply voltages and clock frequencies, and the capability to handle special cells such as level shifters and isolation cells.
Power-aware CTS with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization that ensures a balanced clock tree with the minimum number of clock buffers.
The only architecture that provides seamless concurrent optimization for both power states and timing, covering all operating modes and corners through all stages of the flow.
Unified Power Format (UPF)-based Netlist-to-GDSII flow including support for power state definition tables.
Additionally, the Olympus-SoC product offers techniques such as concurrent multi-Vt optimization, power gating using MTCMOS switch cells, retention flop synthesis, gas station methodology, and power-aware buffering and sizing. The Olympus-SoC system is architected for today’s large, complex low power SoCs with the ability to directly handle 100 million-plus gates in flat mode. Fully-multithreaded analysis engines, and the industry’s only fully-parallelized timing and optimization engine, provide up to 7X speedup on multicore and multi-CPU computing platforms.
“The core innovations that give the Olympus-SoC system a generation lead over other tools in terms of design closure also contribute to its ability to deliver the best low power designs,” said Pravin Madhani, general manager for the Place and Route division at Mentor Graphics. “While all place-and-route tools provide mechanisms to implement low power design strategies, such as multiple clock and voltage domains, and retention registers, only the Olympus-SoC system with concurrent MCMM optimization can ensure the best results across all operational and voltage modes, and across all process and manufacturing variability corners.”
Availability
Olympus-SoC for low power design is available now.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
Mentor Graphics is a registered trademark and Olympus-SoC is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners
For more information, please contact:
Gene Forte
Mentor Graphics
503.685.1193
gene_forte@mentor.com
Sonia Harrison
Mentor Graphics
503.685.1165
sonia_harrison@mentor.com
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