Debugging hybrid FPGA logic/processor designs

Debugging hybrid FPGA logic/processor designs

FPGA-based embedded designs can be instrumented for advanced analysis

BY CRAIG ABRAMSON
Xilinx, San Jose, CA
http://www.xilinx.com

FPGAs continue to advance, enabling ever more integration of programmable technologies into the heart of embedded systems. Today’s high-performance FPGAs boast hundreds of thousands of programmable logic cells, on-chip high-speed serial transceivers, extraordinary levels of embedded memory, and built-in digital signal processing capabilities.

Indeed, these devices can easily contain complete systems, including hard and soft processor cores along with soft peripherals to implement an entire custom processing solution in an FPGA. However, to design and debug robust embedded systems, designers need more than complex silicon. They also need access to hardware and software design tools, intellectual property (IP), and development boards tailored to their design methodology.

Debug of FPGA-based embedded processors is done via JTAG.

Some FPGA vendors are addressing this reality with “targeted design platforms” that take bold steps to refine domain-specific design methodologies and deliver user-specific tool configurations that better serve the diverse needs of embedded, DSP, and hardware designers. These platforms offer access to a wide array of programmable devices supported by open standards, common design flows, IP, sophisticated development tools, and run-time platforms.

Such intelligent, platform-aware tools simplify design and accelerate the embedded development process, with automated wizards that walk users through the design process to reduce errors and ease learning curves, as well as automated design generators to quickly facilitate the creation of custom embedded systems. With the right tools for the job and domain-specific targeted design platforms that reflect the way they work, embedded system designers (both hardware and software) can spend less time developing the infrastructure of an application and more time building differentiating features into their product designs.

FPGA-based advantage

For debug in particular, FPGA-based embedded systems have distinct advantages over ASIC and ASSP designs that rely on conventional verification methodologies with externally probing package pins or board traces. Functional debugging often dominates the “lab phase” of initial system startup, when developers typically deploy their favorite piece of lab test equipment.

However, with their inherent programmability, FPGAs enable a virtually limitless combination of test and debug configurations. In addition, specialized FPGA debug toolsets allow embedded designers to actively monitor and analyze the internal state of logic and embedded functions simultaneously during operation for real-time on-chip verification, including the ability to cross-trigger between hardware and software blocks.

When a soft logic analyzer, a.k.a. an integrated logic analyzer (ILA), is inserted directly into the hardware design, designers no longer need to devote I/O pins to route out internal signals for debug. Instead, these signals are captured in block RAM at system speed and brought out through the JTAG port to a host PC with a logic analyzer GUI for viewing.When a soft logic analyzer, a.k.a.also known as an integrated logic analyzer (ILA), is inserted directly into the hardware design, designers no longer need to devote I/O pins to root out internal signals for debug. Instead, these signals are captured in block RAM at system speed and brought out through the JTAG port to the ILA for increased signal visibility.

By eliminating the need for complex external test fixtures, designers spend less time debugging in-system chip functionality. Better yet, advanced ILA capabilities like multiple trigger inputs, match units, multiple-state trigger sequencing, and expanded sample storage let them use more complex verification and debug strategies that are vital to ensuring rigorous analysis and the highest-quality design.

Integrated instrumentation

FPGA-based embedded designs are also easily instrumented with a fully parameterizeable integrated bus analyzer (IBA) to gain access to system buses that are difficult or impossible to access using traditional methods. Designers can display bus transaction traces alongside logic analyzer traces and view data in a bus cycle-level display complete with time stamps.

They can also time-stamp data samples to facilitate correlation between multiple ILA, IBA cores, or external test equipment. It makes it possible for designers to set a breakpoint on a processor local bus (PLB) address and set the IBA to trigger on that same address to debug both the hardware and software simultaneously.

For example, using the ILA, designers can trigger a hardware event occurring in a DSP core, and then use that trigger to interrupt the processor and have it go into an error recovery routine, perhaps dumping large amounts of data into RAM connected to the FPGA for detailed analysis. This approach to integrated bus analysis sets a new standard for productivity during embedded system debug.

Similarly, software debug of FPGA based embedded processors is done via JTAG using an industry standard Eclipse-based environment. Eclipse forms the foundation many of the microprocessor development environments in use today. The Eclipse framework offers an environment that can be used throughout the entire software development process. It provides among other things, a full-featured, source-level debugger so that application code can be written, compiled, built, downloaded to the processor(s), debugged and profiled, and eventually (if necessary) burnt into a flash PROM all within a single tool.

Wizards simplify hardware/ software co-debug

Designers can leverage the integrated debug tools in a highly automated, streamlined way using wizards to automatically connect the IBA or ILA trigger-out signal directly to the processor. For instance, in a system containing a processor like the MicroBlaze soft-core processor and tools from Xilinx a hardware event can unconditionally halt execution of the processor, enabling control of software execution from a non-embedded portion of the hardware design.

Debug wizards help in the other direction as well, connecting status signals from the processor to the trigger-in of the ILA. During code debug, if a breakpoint is encountered, a processor status signal (in this example the “MB_Halted” signal) is asserted, causing the ILA to trigger. This configuration allows designers to capture the state of hardware anywhere in the FPGA design when a specific software event happens, either inside or external to the processor system.

Debug wizards help in the other direction as well. If a targeted value is reached, or breakpoint encountered, the IBA will trigger. It automatically connects the halt signal along with the current value to the IBA core. This configuration allows designers to capture the state of hardware anywhere in the FPGA design when a very specific set of software events happens, either inside or external to the processor.

Survey after survey affirms that putting a microprocessor in an FPGA is a winning strategy for embedded systems. Now with highly versatile, configurable design and debug tools readily accessible, designers can take full advantage of the FPGA’s high-performance processing capabilities to get embedded systems finished and into production even faster. ■