Timing and synchronization in broadcast video

Timing and synchronization in broadcast video

Here’s how to ensure proper deserialization, processing, and serialization of the video signal

BY JAMES WILSON and DAN GALLANT
Silicon Laboratories, Austin, TX
https://www.silabs.com/

Clock generation and synchronization are becoming increasingly complex in broadcast video applications. In a studio with multiple cameras or other video sources, synchronization is required to simplify downstream video processing such as switching, keying, and editing. This process, otherwise known as genlock, synchronizes all video capture, conversion, editing, and distribution equipment to a master sync generator. A typical video genlock block diagram is shown in Fig. 1 .

Fig. 1. Shown above is a typical video genlock system.

The sync separator extracts timing from a NTSC/PAL/HD Composite video signal. The resulting horizontal sync pulse (HSYNC) provides an accurate frequency reference for the timing generator, which in turn filters unwanted jitter from this signal with a sub-10-Hz loop bandwidth phase-locked loop (PLL) and generates the video-sampling clock. The low-jitter sampling clock is provided to the SD/HD-SDI SerDes, the output of which is genlocked to the master sync generator. Based on this process, all studio equipment can be easily synchronized.

Timing challenges arise due to the wide diversity of video formats, frame rates, HSYNC line rates, and sampling clocks required by modern HD video equipment. Table 1 shows a list of common video formats and their associated HSYNC and sampling rates. Due to the proliferation in the number of video formats and frame rates, modern broadcast video equipment design requires more sophisticated timing architectures and a greater number of components.

Complicating matters, jitter requirements are becoming increasingly more difficult to meet. SMPTE 292M HD-SDI specifies that peak-to-peak jitter must be less than 134 ps while the SMPTE 424M 3G SDI standard mandates that system-level jitter cannot exceed 67 ps peak-to-peak, resulting in jitter requirements that are significantly stricter than legacy SDI and DVI standards.

In addition to video clocks, audio clocks (typically 24.576 MHz) must be generated from the broad range of different video formats/frame rates summarized above. Fortunately, frequency-flexible, low-jitter clock sources are now available that can simplify genlock and asynchronous video/audio clock generation.

Simplifying synchronous clock generation

For synchronization applications, traditional genlock timing generators require a complicated assortment of cascaded phase-locked loops (PLLs), external loop filters, and an external low-jitter voltage-controlled crystal oscillator (VCXO). Special care must be taken during loop filter design and layout to ensure that loop stability requirements are met and to minimize jitter, since the loop filter’s external components are sensitive to board-level noise.

In addition, low-jitter VCXOs may have relatively long lead times, approaching 8 to 14 weeks due to their manufacturing complexity. Due to recent advancements in fine-geometry CMOS technology, new genlock clock IC solutions are now available that provide a fully integrated solution without the necessity of external loop filter and VCXO components.

One of these new genlock solutions is the any-rate jitter-attenuating clock multiplier shown in Fig. 2 . The benefit of using an any-rate clock solution is twofold.

First, a fully integrated PLL solution provides more than 50% lower jitter than was previously available with discrete solutions since all PLL components are integrated on-chip. Second, the any-rate capability of the device makes it possible to synchronize to NTSC or PAL HSYNC rates and generate any HD-SDI or 3G-SDI rate in a single device, eliminating the need for multiple PLLs.

For example, an NTSC-to-HD-SDI application requires a PLL capable of providing a multiplication ratio of 4719000/1001 or 4.71428571428571. Lastly, eliminating multiple cascaded PLLs ensures better jitter performance while minimizing space requirements.

Fig. 2. New genlock IC solutions provide a fully integrated solution without the necessity of external loop filter and VCXO components.

Simplifying asynchronous clock generation

A good example of where an asynchronous clock source is required by broadcast video is the SDI reclocker shown in Fig. 1. The SDI reclocker typically requires an external crystal oscillator or voltage-controlled crystal oscillator (XO/VCXO) as a reference clock for its internal clock and data recovery (CDR) circuitry. Depending on the SDI data rate, this clock reference could be any of the clock rates shown in Table 1.

The traditional approach for generating these clock frequencies has been to use multiple discrete XOs and a mux for selection. As shown in Fig. 3 , the Si534 quad-frequency crystal oscillator simplifies this by generating up to four different clock frequencies from a single 5 x 7-mm package. Frequency selection pins (FSel) are used to determine the frequency of the output clock.

Fig. 3. Multifrequency XOs and clocks simplify clock generation.

Video processors and FPGAs often need several asynchronous clocks to operate their digital functions. Also shown in Fig. 3, the Si5338 I2 C programmable any-rate, any-output quad clock generator synthesizes four simultaneous, independent any-rate clocks up to 350 MHz from a single low-cost crystal. This device is ideally suited for replacing discrete clock oscillators and, since it is fully programmable, it can generate all the frequencies needed to accommodate multiple video rates, including the ability to generate 74.25 MHz, 74.25/1.001 MHz, and other HD rates simultaneously with 0-ppm frequency error. ■

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