Meeting USB 3.0 performance and ease-of-use expectations

Meeting USB 3.0 performance and ease-of-use expectations

Timing and signal integrity issues take a step up with 3.0s a tenfold bandwidth increase

BY JOSEPH SPISAK
Pericom
San Jose, CA
http://www.pericom.com

The tenfold increase in bandwidth that USB 3.0 offers consumers over USB 2.0 brings with it a variety of high-speed signaling issues that designers must address, including increased sensitivity to attenuation and jitter. At the frequencies USB 3.0 operates at, trace, connector, and cabling losses can quickly erode signal quality, making it difficult to ensure reliable communications over low-quality shielded differential pair cables. While OEMs could required the use of higher quality, thicker gauge cabling for their products, such cabling can substantially increase overall cost.

Consumers are used to not having to worry about cable quality when they connect USB devices. However, when a low quality cable is used and performance suffers, they will often assume that the device is at fault, not their marginal hub or low-quality cables that appear to operate well enough with their other peripherals. If early adopters are disappointed with USB 3.0, this will adversely impact market uptake. Therefore, to meet the low-cost and ease-of-use expectations consumers already have for USB 3.0, developers must make maintaining signal quality a point of emphasis.

Chips to the rescue

Reduced signal quality can be regained using advanced transceivers (ReDrivers) to restore, adjust, and retransmit signals (see Fig. 1 ). ReDrivers adjust emphasis and equalization to open up a closed receiver eye. Signal conditioning increases signal margin,and lowers the overall bit error rate. In addition to ensuring reliability, signal conditioning allows for the use of longer, thinner, and lower-quality cables that are more cost-effective, flexible, and aesthetically pleasing. Figure 1 shows three eye diagrams.

Fig. 1. ReDrivers use emphasis, equalization, and idle threshold adjustments to improve signal quality and open signal eyes. Three eye diagrams are shown: (a) at transmitter, (b) at receiver without signal conditioning, (c) at receiver with signal conditioning.

Many manufacturers will meet cost pressures by releasing marginal devices that do not employ signal conditioning. To ensure interoperability with these devices, designs should condition both transmitted and received signals. Further complicating design is the fact that while designers know the drive capability of their transmitter, they usually do not have access to the characteristics of the far-end transmitter.

Improving the signal

Control of the electrical idle threshold provides an excellent means for achieving the optimal receive sensitivity and increase the sensitivity to low signals. This allows longer cables or traces, such as is required in servers or applications like digital TVs where the USB port may be located far from the controller.

Sourcing an accurate clock also plays an important role in maintaining signal quality. As high-frequency clocks tend to be expensive, developers commonly multiply the clock signal from a lower frequency. This also multiplies the clock jitter and significantly cuts into the limited available jitter budget. Engineers must therefore balance input frequency (that is, cost) with induced jitter.

As an example of available solutions, the PI6C557-05 clock generator from Pericom is a low-cost (approx. $1 in volume) IC that provides a 100- or 200-MHz clock and exceeds the stringent jitter requirements of USB 3.0. The clock IC provides 2.2-ps rms phase jitter well under the 3.1-ps requirement.

For improved signal integrity, the PI3EQX7701 or PI3EQX7711 ReDriver ICs feature pin-configured output emphasis control or fully adaptive equalization. The choice here depends on the length of cable or trace length in the channel. These are low-power devices, taking only 220 mW using a 1.2-V supply. ■