Bit-error-rate tester completely checks fastest buses for jitter performance — Agilent Technologies

Bit-error-rate tester completely checks fastest buses for jitter performance — Agilent Technologies

Offering the most complete jitter-tolerance testing for the highest-speed digital interfaces, the J-BERT N4903B serial bit-error-rate tester lets designers create robust products with tighter margins than previously possible, allowing them to accurately characterize and compliance-test next-generation devices based on multi-gigabit serial buses up to 7 or 12.5 Gbits/s.

The instrument can accurately and efficiently characterize QPI, Hypertransport or memory buses as well as receivers, handling both embedded and forward clocking. For embedded clock devices, such as PCI Express, SATA, and USB3, the BERT offers integrated and calibrated jitter sources, with unique PCIe2-compliant two-tone periodic jitter, unique arbitrary and residual SSC, and compliant ISI traces. For 16x Fibre Channel testing, the instrument offers a unique, expanded data-rate range up to 14.2 Gbits/s.

Customers who are using the J-BERT say they’ve experienced significant gains in efficiency because it reduces test setup and complexity. Key to these gains are the instrument’s integrated and calibrated jitter sources (which allow the generation of stress conditions for multiple serial bus interfaces), the variable output levels and rates on data and clock signals, the pattern sequencer for simplified setup of training sequences, automated jitter tolerance test routines, and fast total-jitter and eye-measurement routines.

Agilent Technologies , Santa Clara , CA
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http://www.agilent.com