Next-gen 3G/4G/LTE base station platforms

Base station designs may require a system-on-chip approach

BY ALAN TAYLOR
Mindspeed Technologies
Newport Beach, CA
http://www.mindspeed.com

The mobile broadband industry faces difficult challenges. Operators must cost-effectively meet growing consumer demand for mobile services, using limited available radio-spectrum resources. The good news is that new radio-access technologies are extending the efficiency of that limited spectrum. However, these technologies need significantly higher computational requirements as compared to 2G and 3G.

The industry must move quickly to solve these challenges. The ITU reported in October 2009 that the number of mobile broadband users was expected to pass 600 million last year, and grow at a rate of 50% annually for the next few years.

The Cellular Telephone Industries Association (CTIA) has said that, on average, more than 4 billion text messages are sent daily over the air in the U.S. Verizon, NTT DoCoMo, and China Mobile have each announced plans to launch long-term evolution (LTE) services in 2010 and 2011. Meanwhile, Clearwire and other WiMAX operators have already begun deployment.

Solving 3G/4G/LTE base station challenges may require a system-on-chip approach that combines multiple task-oriented processing engines to handle higher throughput, associated higher RF interferences, and significantly more complex broadband-processing needs. SoCs have the potential to deliver a scalable solution across the full range of femto to macro cell platforms, along with lower system latency, cost, and power consumption.

Base stations processing

The next-generation base stations must support all standards-based services at full throughput. They must support multiple radio-access technologies including 3G and 2G, and they must be future-proofed for evolving requirements.

Things were easier for designers of wire-line infrastructure equipment – higher bandwidth was achieved simply by adding more cables. In contrast, the wireless industry has had to re-invent itself many times over the past 20 years.

The current transition to 3G/4G broadband wireless services was precipitated by demand for broadband mobile Internet services. Unlike the wire-line Internet world, where cost per bit is very low or “free,” the wireless broadband world must significantly reduce costs per bit in order to drive market adoption.

Next-generation radio-access technologies also must reduce end-to-end latency. Voice conversations cannot be supported with satisfactory quality of service using 3G technologies. Voice conversations require end-to-end latency of no more than 150 ms, whereas 3G technologies have an average latency of 200 ms or more. As a result, voice is still carried primarily over the 2G/2.5G infrastructure an extremely inefficient use of spectrum.

Once 3G and 4G networks achieve lower latencies, it will also be possible for them to support popular applications such as interactive gaming. NTT DoCoMo has reported that, by achieving an end-to-end data network latency of no greater than 10 ms, wireless operators could open up a significant new revenue stream by addressing the lucrative interactive gaming market.

Finally, the next generation of 3G/4G radio-access technologies must also coexist with multiple previous technology generations. Handheld devices that only support older technologies must still be adequately supported by newer technologies as they become available, without requiring multiple sets of equipment at each cell site. The key to all of the above capabilities is generating the robust yet power-efficient horsepower to handle a dramatically increased level of 4G baseband processing complexity.

Processing complexity

Today’s 3G computational load comes primarily from very simple correlations, and today’s DSP solutions are tailored for that complexity level. In contrast, the spectrum-efficient radio-access technologies used with 4G standards to improve data-service cost-per-bit also increase required radio transmission power, which can generate unwanted interferences.

Mitigating these requires advanced DSP techniques, and the higher data throughput also creates the need for higher computational complexity in the baseband processing, primarily for Fast Fourier transform (FFT)/inverse FFT (iFFT). Future 4G systems such as LTE and WiMAX will require computational complexity at least one order of magnitude greater than that of 3G systems.

Although DSP technologies continue to improve, they haven’t kept up with 3G/4G wireless baseband processing needs. As a result, manufacturers are turning to multiple DSPs or SoCs plus one or more significant FPGAs (see Fig. 1 ). This has obvious drawbacks, including high system cost and power consumption, the need for multichip task partitioning, longer time to market, more system latency from intradevice data transfers, and cumbersome software maintenance moving forward.

Fig. 1. 3G wireless baseband processing is currently implemented using many general-purpose devices in complex system designs.

Alternatively, a multicore SoC approach can be used to accommodate 4G’s increased computational load while supporting legacy system needs. This new breed of compact, cost-effective, and power-efficient DSP/SoC can use multiple task-oriented processing engines to deliver dramatic increases in computational performance (see Fig. 2 ).

Fig. 2. A Task Dispatcher simplifies the programming model and abstracts away SoC complexities.

Tasks can be partitioned between the best choices of processing technology: general-purpose DSP cores for complex algorithms such as speech compression, channel estimation, etc; RISC processors for control or protocol layer processing; and ASIC or coprocessors for computationally intensive yet algorithmically simple or fixed applications.

This multicore approach also benefits from continuing reductions in transistor geometry, and from the advantages of the now-mature 45/40-nm manufacturing process. The designer will be able to either shrink the size of DSP/SoCs, or integrate more elements into the same footprint. For instance, one key function that SoCs can incorporate is an optimized I/O capability that enables concurrent use of both common public radio interface (CPRI), PCIe, and serial rapid IO (sRIO) interfaces. Another function that can be integrated is IEEE 1588 version 2 clock recovery, along with a built-in ciphering engine for radio interface and backhaul. Built-in power management capabilities can be included, ensuring that various SoC processing operations can be clocked down to reduce power consumption during low-traffic periods.

SoCs with multiple processing engines

One example of a multicore SoC tailored for baseband processing in 3G/4G/LTE base stations is Mindspeed’s Transcede 4000 family, which can be used to develop base station platforms ranging from a “picocell on a chip” to larger macrocell platforms. Using a mix of programmable DSPs and task-specific hardware-acceleration elements, the Transcede family supports the full range of 4G standards, including LTE-FDD, LTE-TDD and WiMax 802.16d, 16e and 16m, as well as 3G standards like W-CDMA (WCDMA, HSPA and HSPA+) or TD-SCDMA.

With typical power consumption of no greater than 15 W, the family offers a more-power-efficient alternative to DSPs with companion FPGAs, while supporting LTE or WiMAX Layers 1 and 2 processing needs for up to three sectors of 20 MHz for 2 x 2 single-input multiple-output (SIMO) antenna systems.

Next-generation 3G/4G/LTE SoCs for base station baseband processing ideally will use a scalable hardware architecture that enables the same software to be used not only for macrocell, microcell, and picocell designs, but also for derivative, low-cost femtocell designs. These processors will also need to have ample DSP headroom for future feature addition/evolution. They will need to solve the problem of managing various processes for maximum efficiency and minimum software complexity. One way to solve this problem is to use a single-threaded simplified programming model. A hardware abstraction mechanism can eliminate the need to partition hardware resources in a traditional static manner.

With this type of programming model, designers can use standard C programming tools to add proprietary value in areas like interference mitigation, beam forming, and channel estimation. This programming is fully decoupled from the underlying hardware, which enables software portability and simplified maintenance. The use of embedded trace capture also provides complete visibility into program flow allowing for non-intrusive real-time debug and optimization. ■