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Evatronix & LFoundry partnership

Evatronix SA (www.evatronix-ip.com), a silicon intellectual property (IP) provider and LFoundry (www.lfoundry.com), an analog / mixed signal silicon foundry with a 200-mm production line based in Landshut, Germany announced recently an agreement to support most popular products from the Evatronix IP portfolio within the LFoundry leading analog / mixed signal technology nodes. The partnership will allow customers to easily apply Evatronix IP to LFoundry’s process design kits (PDK) in both 150 nm and 350 nm technology platforms. This will allow development of analog / mixed signal products especially for European SoC developers.

LFoundry customers will be offered such popular components as the fastest and the smallest 8051 microcontrollers, USB 2.0 High Speed, NAND Flash and SDIO memory controllers as well as the Gigabit Ethernet MAC. Upon customer’s request, any other Evatronix IP can be customized to a desired LFoundry process.

Physical design solution qualified by TSMC for 40 nm

ATopTech (www.atoptech.com), a leader in IC physical design solutions recently announced that Aprisa, the company’s physical design solution, has been qualified for TSMC’s 40-nm technology node, meeting the foundry’s requirements of placement, routing and transparent half node implementation.

Aprisa is a complete netlist-to-GDSII physical design solution, including floorplanning, placement, clock-tree synthesis and optimization, global and detailed routing, and an advanced, extremely fast timing engine to solve the complex timing issues associated with on-chip variation (OCV) and multiorner, multimode (MCMM) analysis.

Based on the company’s Precision Optimization technology, Aprisa enables real design closure at smaller geometries through accurate timing correlation to industry sign-off tools. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process and avoid the exploding runtime issues associated with the variability in submicron designs.