16-bit 80-MSPS ADC offers lowest power, reduced noise

16-bit 80-MSPS ADC offers lowest power, reduced noise

The 16-bit no-missing-codes 80-Msample/s A/D converter (ADC) dissipates 89 mW, which is claimed to be less than half the power of competing 16-bit solutions. The device integrates two useful features for reducing digital feedback: alternate bit polarity mode and a data output randomizer.

The ADC operates from a 1.8-V analog supply and features an SNR performance of 73.1 dB and an SFDR of 88 dB in baseband. Additional features include CMOS, DDR CMOS or DDR LVDS outputs, an 800-MHz full-power bandwidth S/H, and a 0.17-psRMS jitter which allows undersampling of IF frequencies with excellent noise performance.

Housed in a 6 x 6-mm QFN package, the LTC2259-16 includes a clock duty cycle stabilizer circuit to facilitate non-50% clock duty cycles, programmable digital output timing, programmable LVDS output current and optional LVDS output termination. It also offers shutdown and nap modes, as well as a serial SPI port for configuration. (From $35 ea/1,000 — available now.)

Linear Technology , Milpitas , CA
Sales Office 408-428-2050
http://www.linear.com