Audio/video clock generator eliminates need for external clock conditioning

Audio/video clock generator eliminates need for external clock conditioning

The LMH1983 triple-rate (3G/HD/SD) audio/video clock generator eliminates the need for external clock conditioning in professional and broadcast video equipment. It is claimed to provide the industry’s lowest output jitter 40 ps peak-to-peak enabling Society of Motion Picture and Television Engineers compliance using FPGA SerDes transceivers.

The part replaces three external PLLs, VCXOs, and loop filters to simplify design and reduce BOM cost. It generates four simultaneous LVDS clocks with dedicated top-of-frame timing pulses, providing a “plug-and-play” solution with minimal FPGA programming. It also eliminates the time-consuming PLL tweaking and supports SMPTE SDI video and digital audio AES3/EBU standards for 1080p HD video cameras and video capture, conversion, processing, editing, and distribution equipment.

The LMH1983 features automatic input format detection, simple programming of multiple A/V output formats, genlock or digital free run modes, and override programmability of various automatic functions. The recognized input formats include HVF syncs for the major video standards: 27-MHz, 10-MHz, and 32/44-, 1/44.1/48/96-kHz audio word clocks.

Offered in a 40-pin LLP package, the device’s dual-stage PLL architecture integrates four PLLs with three on-chip VCOs. It includes an I2 C-compatible bus interface for programming device registers and reading device status. ($16 ea/1,000 available now.)

National Semiconductor , Santa Clara , CA
Sales 800-272-9959

http://www.national.com