Agilent Technologies Offers Industry’s First Automatic IBIS-AMI Model Generation Capability in an ESL Design F

Agilent Technologies Offers Industry’s First Automatic IBIS-AMI Model Generation Capability in an ESL Design Flow

Models Allow Creation of Ultra-Low BER Contours in Seconds

SANTA CLARA, Calif., June 14, 2010 — Agilent Technologies Inc. (NYSE: A) today announced that its SystemVue Electronic System-Level (ESL) design software, version 2010.07, will automatically generate IBIS Algorithmic Modeling Interface (IBIS-AMI) models. IBIS-AMI, a modeling standard for serializer-deserializer (SerDes) transceivers, was created to enable fast, statistically significant analysis of high-speed digital chip-to-chip links. For the first time, IC manufacturers will be able to automatically generate IBIS-AMI models for their chips as a natural outcome of an ESL workflow.

“IC vendors are adopting IBIS-AMI models because unlike proprietary encrypted models, IBIS-AMI models are ‘write once, run anywhere’ and therefore avoid duplication of effort,” said Colin Warwick, signal integrity application manager with Agilent’s EEsof EDA organization.

Since the IBIS-AMI models are compatible with statistical channel simulators, they allow customers to create ultra low BER contours in seconds, rather than the days or weeks it would take with a netlist model. The drawback used to be that AMI models were hard to create. With SystemVue 2010.07, models are compiled directly and automatically from the exact same ESL model used to specify the original implementation.

“The ability to generate AMI models in SystemVue without having to hand-code in C is an exciting prospect,” said Manuel Luschas, signal integrity manager, Netlogic Microsystems. “Even more compelling is that we can now quickly explore the SerDes design space at the algorithmic level in an ESL design flow. Previously, we would have had to do such exploration at the implementation level where revisions are painfully slow.”

High-speed digital chip I/O pins are increasingly making use of sophisticated signal-processing techniques (e.g., pre-emphasis, adaptive equalization and clock-data recovery phase-locked-loops). This technique helps to mitigate impairments due to chip-to-chip connection. To use the new I/O capabilities to their fullest extent, signal integrity engineers require accurate models of the IC that can be used for system simulation in their EDA tools. The models act like an “executable datasheet” for the IC.

Design and verification of chips with high-speed digital SerDes transceivers is one of the applications that will benefit from Agilent’s SystemVue IBIS-AMI model generation capability. SerDes transceivers are found in almost all consumer and enterprise digital products produced today, from laptop computers and data center servers to telecommunication switching centers and Internet routers. The timely availability of the SystemVue generated models will help manufacturers of these products arrive at an optimum design through rapid and complete exploration of the design space. Unlike proprietary channel simulators offered by some IC vendors, EDA tools like Agilent’s Advanced Design System allow ‘mix and match’ modeling, for example, a transmitter from one IC vendor and a receiver from another.

Agilent’s SystemVue is a leading EDA environment for ESL design. For a free information package on SystemVue in AMI applications, visit www.agilent.com/find/eesof-ami-model-gen or contact your local Agilent representative.

U.S. Pricing and Availability

Agilent’s SystemVue 2010.07 with AMI Modeling Toolkit will be available as a customized solution in the third quarter of 2010. Contact your local representative for pricing. A high-resolution image of Agilent’s SystemVue is available at www.agilent.com/find/SystemVue2010_W1714_AMI_Generator_images.

www.agilent.com/find/eesof