Microcontrollers with real-time advantages

Some available MCUs have special ways to keep latency low and response fast

BY JIM HARRISON
West Coast Editor

You can make the most powerful CPU possible, but if you can’t connect to the outside world efficiently, it’s all for naught. This is especially true for real-time systems that can’t afford to wait around to get bytes out.

Some processor folks have implemented what’s often called event management. This takes the communication load off of the CPU, normally driven by an interrupt. That interrupt usually takes on the order of 20 to 50 clock cycles; by the time the processor saves the context for a limited number of registers, accesses a peripheral, saves the data, restores the context, and perhaps deals with a pipeline flush.

But a single interrupt is not so bad. Multiple interrupts cause bigger problems for designers because determinism takes a big hit. When many interrupts happen at the same time latency jumps up. For example, say that during your interrupt a higher-priority interrupt occurs and it takes 75 cycles, adding to the latency of the first interrupt. Latency now ranges from 50 to 125 cycles for the lower-priority task. And if you have even more high-priority interrupts, determinism is gone.

The interrupt latency is usually defined by manufacturers as a time interval between the instance when interrupt is recognized and the instance when the first instruction of the ISR is executed. On simple MCUs, this might be simple. But on larger MCUs, if the interrupt occurs while a multicycle instruction is in process, it won’t get recognized for a while, and that can add cycles. Multiply instructions can take dozens of clocks and read-modify-write instructions like “increment memory” inherently take some time.

Also, it is not just response time but how much load we add to the CPU. So the execution of that interrupt and the then return to the main stream can take a lot of CPU time. You then either speed up the MCU or find another way to do these tasks when your program breaks. And there is some software around that disables interrupts – which can definitely throw a wrench into the works.

MCUs with an event management system do not use interrupts for handling peripherals. This kind of a system triggers peripherals and can be triggered by peripherals.

Atmel’s system

For example, the Event System on the 32-bit AT32UC3xxx and the 8-bit ATxmegaxxx processors from Atmel allows inter-peripheral communication to take place without CPU intervention and guarantees two-cycle latency between the completion of one peripheral operation and the start of another. This will reduce or eliminate the jitter and unpredictable latency associated with a traditional CPU interrupt.

Now this method uses DMA for the data transfer, so the main bus is still used and thus if the CPU wanted to perform a task with data movement it might find the bus was busy. But, to save power you could put the CPU to sleep while the Event System was taking care of peripheral I/O.

An additional effect of reducing the number of concurrent interrupts is the ability to maintain a smaller stack. As each interrupt must perform a context save by pushing potentially dozens of registers to the stack, eliminating several layers of context significantly cuts memory use.

Atmel gives an example of a 2-Mbit/s UART or SPI interface that takes 1% of the CPUs time using its Event System and DMA and 57% using the CPU instead.

Renesas has a system

Renesas has what it calls the DTC (Data Transfer Controller) and the ELC (Event Link Controller). DTC is essentially table driven DMA. It uses a separate interrupt controller and can have many channels operating at once and transfers data between memories without using the CPU. It is used to take noncritical stuff off the CPU and usually does not aid real-time response.

The Renesas Event Link Controller, on the other hand, can help real-time response. It allows events output from peripheral functions to be linked to event inputs on different peripheral functions and can have (usually) 22 sources × 7 types of event-link operations. Events can start up a software module independently from interrupt requests, even while the CPU is in sleep mode.

The company’s latest MCU targeting real-time control is the 16-bit RL78 series ( www2.electronicproducts.com/-article-HLJH04_Aug2011.html.aspx). These ICs have DTC and ELC, dual 64-MHz-capable 16-bit timer units for precise control of low-end motor systems, and multiply/divide and multiply/accumulate instructions. They operate from 40° to 85°C.

ARM architectures

Now ARM-based MCUs can have similar architectural features via the AMBA specification and the NIC-301 Interconnect IP but it depends in the implementation. The AMBA interface specification allows chip makers to produce networks of connections on chip where the peripherals can connect to the memory, either on chip or off chip through a memory controller.

The AMBA specification says nothing about the connection topology; that’s the job of the system designer. The spec allows “masters” to initiate transfers by requesting read data from an address or delivering write data with an address.

The on-chip interconnect then routes the data to or from the appropriate location. ARMs NIC-301 Interconnect IP allows its customers to build high-performance interconnects quickly. It allows connections across a chip, linking (in theory) any number of masters to any number of slaves through the careful use of hierarchical switches. On ARM-based SoCs, it is extremely common for peripherals to transfer data either directly or via a separate DMA engine to memory with the processor intervening only on interesting event boundaries initiated by interrupts.

Keith Clarke, vice president and general manager of the Fabric IP and Processor Division at ARM, said that on ARM-based SoCs, it is extremely common for peripherals to transfer data either directly or via a separate DMA engine to memory, with the processor intervening only on interesting event boundaries initiated by interrupts. Thus the processor can stay asleep while high-speed data transfers happen across the chip and off chip. ■

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