RTOS facilitates MCU power management

Power-aware real-time operating systems take full advantage of available hardware facilities

BY ARVIND RAGHURAMAN
Embedded Software Engineer
Mentor Graphics
www.mentor.com
and
MIGUEL MORALES
Marketing Manager
Stellaris ARM Cortex-M
Texas Instruments
www.ti.com

A pervasive trend in the embedded space today is the relentless demand for increased end-device functionality. The advent of 32-bit microcontrollers with enhanced features such as network connectivity and advanced human-machine interfaces has drastically increased the processing power and functional capability available to MCU-based devices. System designers today are taking advantage of this development to design fully functional, feature-rich applications. However, they still face challenges when it comes to optimizing devices to operate within tight power budgets imposed by battery life and heat dissipation constraints of the system.

In order to help designers optimize systems for power-efficiency, silicon vendors provide various hardware facilities to optimize and manage MCU power consumption. Power-aware real-time operating systems, such as the Nucleus RTOS from Mentor Graphics, take full advantage of these hardware facilities and provide built-in power management capabilities that enable developers to effectively drive MCU power consumption from application level. It’s important that system designers have a good understanding of what an RTOS can do for them for application-driven power management.

There are four key aspects to reducing MCU power consumption. The first two — process technology and IC design — are managed by silicon vendors. The last two — application-driven power management (enabled by a power-aware RTOS) and system-level design (that is, the placement of other electronic components) — are under the control of the system designer.

Process technology/IC design for optimized power

Process technology has traditionally been the means for reducing power consumption in an MCU, since shrinking a design and lowering its internal voltage yields significant savings. For example, TI’s Stellaris LM4F Cortex-M4 based microcontroller implemented in a 65-nm process balances high performance (up to 80 MHz plus an FPU) with good power efficiency (375 μA/MHz active, standby modes as low as 1.6 μA) to provide superior efficiency compared to previous generations.

Silicon vendors have developed innovative IC design techniques to create distinct power domains within the MCU and enable various low-power operating modes. This allows developers to shut down those sections of the MCU that are not in use, based on the dynamic needs of the application.

Some architectures even integrate hibernate blocks with a completely independent voltage domain from the rest of the microcontroller. These hibernate blocks enable very low power consumption by including only the minimum number of gates required (such as a low-frequency oscillator, a real-time clock, a small amount of RAM to save state, and a wakeup mechanism to exit from hibernate) to keep the system “breathing” on a backup battery.

Fig. 1: Silicon vendors have made significant progress in minimizing “wake time” to improve power efficiency.

A system will consume the most power in active state. The faster the system can complete its tasks and transition to a low-power mode, the more efficient it will be (see Fig. 1a ). Transitioning to low-power modes causes systems to suffer losses. The CPU takes time and power to transition between power modes (see Fig. 1b ).

Developers can minimize mode switching losses by reducing switching frequency. Silicon manufacturers further improve power efficiency by reducing the actual mode transition time. For example, the Stellaris LM4F microcontroller series supports wake times as fast as 500 μs. For ultra-low-power applications that can operate under 30 MHz, TI’s 16-bit MSP430 MCU family can achieve operation at less than 1 μA with a 5-μs wakeup.

The importance of a power-aware RTOS

With the addition of network connectivity and advanced HMI functionality, even simple applications are no longer single-threaded systems. To coordinate operation, as well as maximize use of an MCU’s low-power architectural capabilities, applications need a power-aware RTOS.

An RTOS-based design provides two key advantages for developing power-efficient applications. First, the multi-threaded application model enabled by using an RTOS provides an enabling framework to switch the system to low-power operating modes during system idle time. Second, a power-aware RTOS equips developers with proven, well abstracted, ready-to-use APIs for application-level control of peripheral power states, system power states, and operating voltage and frequency.

Optimizing dynamic power consumption

During periods of low or no system activity, the low-power modes provided by the MCU can be effectively exploited by the operating system to achieve run-time power savings. In addition to switching the MCU to low-power mode, other power-hungry blocks present in the system can be transitioned to low-power operating states to maximize power savings.

For example, SDRAM modules can be put in self-refresh mode during long periods of inactivity. An OS scheduler can make intelligent decisions on the best low-power state to switch to, based on the expected system idle time and power cost of switching in and out of the low-power state — as compared to the expected power savings.

Note that the calculated power savings may not be fully realized if the CPU is frequently interrupted during idle time. Figure 2a illustrates the power savings achieved by placing CPU in idle mode and SDRAM in self-refresh mode during system idle time.

Fig. 2a: Power savings achieved by Nucleus when transitioning to low-power states in idle time.

Techniques such as OS tick suppression can be used to prolong the duration of CPU idle time, thereby multiplying idle-time power savings. Typical real-time kernels use a periodic OS tick timer interrupt to evaluate internal state and to make scheduling decisions. Tick suppression enables the kernel to dynamically change the time period of the OS tick timer interrupt based on the expected idle time, enabling the system to stay in low-power modes for longer periods of inactivity. Figure 2b illustrates OS tick profiles with and without tick suppression enabled.

Fig. 2b: The Nucleus RTOS can provide a 50x reduction in tick frequency during periods of system inactivity.

For longer periods of system inactivity, such as when a device can go into hibernation mode, RTOS systems will use any hibernate facilities provided by hardware to save and restore system state. Most applications require the peak processing capability of the underlying CPU for only a small percentage of its operational time. Considerable power savings can be obtained using dynamic frequency and voltage-scaling (DVFS) techniques. The system developer can make application-level decisions to pick an optimal operating point depending on the functionality required. A switch from one operating point to another requires:

1. all concerned peripherals be notified of the operating point change request

2. peripheral activity be stopped

3. CPU clock, bus clocks, and peripheral clocks be changed for the new operating point

4. CPU and peripheral activity be resumed

A power-aware RTOS should abstract these details and enable the user to make application level DVFS decisions.

Optimizing static power consumption

Static power consumption in a system can be directly attributed to the number of peripheral blocks that are active (clocked and powered ON) at a given point in time. Although powering off peripherals that are not being used sounds fairly simple, the implementation details of safely switching between peripheral power states during run-time in a multi-threaded environment could get complicated.

Fig. 3: Illustration of power savings achieved by system power state control.

Power-aware RTOSs abstract these implementation details and enable developers to make high-level decisions on peripheral power states. Figure 3 illustrates a hypothetical MP3 player leveraging Nucleus RTOS system power states to optimize static power consumption. ■